12.1 Layout Guidelines

For the PCB design to be successful, start with the design of the protection and filtering circuitry because ESD and EFT transients have a wide frequency bandwidth from approximately 3-MHz to 3-GHz and high frequency layout techniques must be applied during PCB design. On chip IEC ESD protection is good for laboratory and portable equipment but is usually not sufficient for EFT and surge transients occurring in industrial environments. Therefore, robust and reliable bus node design requires the use of external transient protection devices at the bus connectors. Placement at the connector also prevents these harsh transient events from propagating further into the PCB and system.

Use V_CC and ground planes to provide low inductance.

Design the bus protection components in the direction of the signal path. Do not force the transient current to divert from the signal path to reach the protection device. Below is a list of layout recommendations when designing a CAN transceiver into an application.

• Transient Protection on CANH and CANL: Transient Voltage Suppression (TVS) and capacitors (D1, C5 and C7 shown in Figure 23) can be used to protect the system level transients like EFT, IEC ESD, and Surge. These devices must be placed as close to the connector as possible. This prevents the transient energy and noise from penetrating into other nets on the board.
• Bus Termination on CANH and CANL:Figure 23 shows split termination where the termination is split into two resistors, R5 and R6, with the center or split tap of the termination connected to ground through capacitor C6. Split termination provides common mode filtering for the bus. When termination is placed on the board instead of directly on the bus, care must be taken to ensure the terminating node is not removed from the bus, as this causes signal integrity issues if the bus is not properly terminated on both ends.
• Decoupling Capacitors on V_CC and V_RXD: Bypass and bulk capacitors must be placed as close as possible to the supply pins of transceiver (examples are C2, C3, C5, and C6).
• Ground and power connections: Use at least two vias for V_CC, V_IO, and ground connections of bypass capacitors and protection devices to minimize trace and via inductance.
• Digital inputs and outputs: To limit current of digital lines, serial resistors may be used. Examples are R1, R2, R3, R4, and R5.
• Filtering noise on digital inputs and outputs: To filter noise on the digital I/O lines, a capacitor may be used close to the input side of the I/O as shown by C1 and C4.
• External pull-up resistors on input and output pins: Because the internal pullup and pulldown biasing of the device is weak for floating pins, an external 1-kΩ to 10-kΩ pullup or pulldown resistor must be used to bias the state of the pins during transient events.
• Fault Output Pin (SN65HVD257 only): Because the FAULT output pin is an open drain output, an external pullup resistor is required to pull the pin voltage high for normal operation (R5).
• V_RXD Supply (SN65HVD256 only): The SN65HVD256 device will need additional bypass capacitors for the V_RXD supply shown with C5 and C6.
• TXD input pin: If an open-drain host processor is used to drive the TXD pin of the device, an external pullup resistor between 1 kΩ and 10 kΩ must be used to help drive the recessive input state of the device (weak internal pullup resistor).

12.2 Layout Example

Figure 23. Layout Example