SGLS367E September   2006  – September 2015 SN65HVD30-EP , SN65HVD33-EP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Driver
    6. 6.6  Electrical Characteristics: Receiver
    7. 6.7  Switching Characteristics: Driver
    8. 6.8  Switching Characteristics: Receiver
    9. 6.9  Receiver Equalization Characteristics
    10. 6.10 Dissipation Ratings
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Low-Power Standby Mode
      2. 8.3.2 Driver Output Current Limiting
      3. 8.3.3 Hot-Plugging
      4. 8.3.4 Receiver Failsafe
      5. 8.3.5 Safe Operation With Bus Contention
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Parameter Measurement Information

SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP SN65HVD35-EP pmi_dr_circ_lls665.gif Figure 10. Driver VOD Test Circuit and Voltage and Current Definitions
SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP SN65HVD35-EP pmi_dr_lls665.gif Figure 11. Driver VOD With Common-Mode Loading Test Circuit
SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP SN65HVD35-EP pmi_vodring_lls665.gif Figure 12. VOD(RING) Waveform and Definitions

VOD(RING) is measured at four points on the output waveform, corresponding to overshoot and undershoot from the VOD(H) and VOD(L) steady state values.

SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP SN65HVD35-EP pmi_test_lls665.gif
Input: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
Figure 13. Test Circuit and Definitions for Driver Common-Mode Output Voltage
SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP SN65HVD35-EP pmi_dr_sw_lls665.gif
A. Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
Figure 14. Driver Switching Test Circuit and Voltage Waveforms
SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP SN65HVD35-EP pmi_dr_hi_lls665.gif
A. Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
B. CL Includes Fixture and Instrumentation Capacitance
Figure 15. Driver High-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP SN65HVD35-EP pmi_dr_low_lls665.gif
A. Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
Figure 16. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP SN65HVD35-EP pmi_rec_vo_lls665.gif Figure 17. Receiver Voltage and Current Definitions
SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP SN65HVD35-EP pmi_rec_sw_lls665.gif
A. CL Includes Fixture and Instrumentation Capacitance
B. Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
Figure 18. Receiver Switching Test Circuit and Voltage Waveforms
SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP SN65HVD35-EP pmi_rec_circ_lls665.gif
A. Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
Figure 19. Receiver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP SN65HVD35-EP pmi_rec_time_lls665.gif
A. Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
Figure 20. Receiver Enable Time From Standby (Driver Disabled)
SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP SN65HVD35-EP pmi_vtest_lls665.gif Figure 21. Test Circuit, Transient Over Voltage Test