SLLS665M September   2005  – February 2023 SN65HVD30 , SN65HVD31 , SN65HVD32 , SN65HVD33 , SN65HVD34 , SN65HVD35

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
    1.     6
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: Driver
    6. 7.6  Electrical Characteristics: Receiver
    7. 7.7  Device Power Dissipation – PD
    8. 7.8  Supply Current Characteristics
    9. 7.9  Switching Characteristics: Driver
    10. 7.10 Switching Characteristics: Receiver
    11. 7.11 Dissipation Ratings
    12. 7.12 Typical Characteristics
      1.      Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Low-Power Standby Mode
      2. 8.3.2 Driver Output Current Limiting
      3. 8.3.3 Hot-Plugging
      4. 8.3.4 Receiver Failsafe
      5. 8.3.5 Safe Operation With Bus Contention
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.1 Low-Power Standby Mode

When both the driver and receiver are disabled (DE is low and RE is high), the device is in standby mode. If the enable inputs are in this state for less than 60 ns, the device does not enter standby mode. This guards against inadvertently entering standby mode during driver or receiver enabling. The device in standby mode only when the enable inputs are held in this state for 300 ns or more. In this low-power standby mode, most internal circuitry is powered down, and the supply current is typically less than 1 nA. When either the driver or the receiver is re-enabled, the internal circuitry becomes active.

GUID-86F2D197-C1B9-4FB1-A34E-DF79F91196D8-low.gifFigure 8-1 Low-Power Standby Logic Diagram

If only the driver is re-enabled (DE transitions to high) the driver outputs are driven according to the D input after the enable times given by tPZH2 and tPZL2 in the driver switching characteristics. If the D input is open when the driver is enabled, the driver output defaults to Y low and Z high, in accordance with the driver-failsafe feature.

If only the receiver is re-enabled ( RE transitions to low) the receiver output is driven according to the state of the bus inputs (A and B) after the enable times given by tPZH2 and tPZL2 in the receiver switching characteristics. If there is no valid state on the bus the receiver responds as described in the failsafe operation section.

If both the receiver and driver are re-enabled simultaneously, the receiver output is driven according to the state of the bus inputs (A and B) and the driver output is driven according to the D input. Note that the state of the active driver affects the inputs to the receiver. Therefore, the receiver outputs are valid as soon as the driver outputs are valid.