SLLS665M September   2005  – February 2023 SN65HVD30 , SN65HVD31 , SN65HVD32 , SN65HVD33 , SN65HVD34 , SN65HVD35

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
    1.     6
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: Driver
    6. 7.6  Electrical Characteristics: Receiver
    7. 7.7  Device Power Dissipation – PD
    8. 7.8  Supply Current Characteristics
    9. 7.9  Switching Characteristics: Driver
    10. 7.10 Switching Characteristics: Receiver
    11. 7.11 Dissipation Ratings
    12. 7.12 Typical Characteristics
      1.      Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Low-Power Standby Mode
      2. 8.3.2 Driver Output Current Limiting
      3. 8.3.3 Hot-Plugging
      4. 8.3.4 Receiver Failsafe
      5. 8.3.5 Safe Operation With Bus Contention
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.4.1 Layout Guidelines

Robust and reliable bus-node design often requires the use of external transient protection devices to protect against EFT and surge transients that can occur in industrial environments. Because these transients have a wide frequency bandwidth (from approximately 3 MHz to 3 GHz), high-frequency layout techniques must be applied during PCB design.

  • Place the protection circuitry close to the bus connector to prevent noise transients from entering the board.
  • Use VCC and ground planes to provide low-inductance. High-frequency currents follow the path of least inductance and not the path of least impedance.
  • Design the protection components into the direction of the signal path. Do not force the transients currents to divert from the signal path to reach the protection device.
  • Apply 100-nF to 220-nF bypass capacitors as close as possible to the VCC pins of transceiver, UART, and controller ICs on the board.
  • Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to minimize effective via inductance.
  • Use 1-kΩ to 10-kΩ pullup or pulldown resistors for enable lines to limit noise currents in these lines during transient events.
  • Insert series pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into the transceiver and prevent it from latching up.
  • While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide varistors (MOVs), which reduces the transients to a few hundred volts of clamping voltage and transient blocking units (TBUs) that limit transient current to 200 mA.