SLLS666F September   2005  – March 2023 SN65HVD50 , SN65HVD51 , SN65HVD52 , SN65HVD53 , SN65HVD54 , SN65HVD55

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Available Options
  6. Pin Configurations
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Recommended Operating Conditions
    3. 7.3 Electrostatic Discharge Protection
    4. 7.4 Driver Electrical Characteristics
    5. 7.5 Driver Switching Characteristics
    6. 7.6 Receiver Electrical Characteristics
    7. 7.7 Receiver Switching Characteristics
    8. 7.8 Thermal Characteristics
    9. 7.9 Typical Characteristics
  8. Parameter Measurement Information
  9. Device Information
    1. 9.1 Ll-Power Standby Mode
    2. 9.2 Function Tables
    3. 9.3 Equivalent Input and Output Schematic Diagrams
  10. 10Application and Implementation
    1. 10.1 Thermal Characteristics of IC Packages
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Receiver Switching Characteristics

over recommended operating conditions unless otherwise noted
PARAMETERTEST CONDITIONSMINTYP(1)MAXUNIT
tPLHPropagation delay time, low-to-high-level outputHVD50, HVD53VID = -1.5 V to 1.5 V,
CL = 15 pF,
See Figure 8-9
2440ns
HVD51, HVD52, HVD54, HVD554355
tPHLPropagation delay time, high-to-low-level outputHVD50, HVD532635
HVD51, HVD52, HVD54, HVD554760
tsk(p)Pulse skew (|tPHL - tPLH|)HVD50, HVD535
HVD51, HVD547
tsk(pp)(2)Part-to-part skewHVD50, HVD535
HVD51, HVD546
HVD52, HVD556
trOutput signal rise time2.34
tfOutput signal fall time2.44
tPHZOutput disable time from high levelDE at 3 V, CL = 15 pF
See Figure 8-10
17
tPZH1Output enable time to high level10
tPZH2Propagation delay time, standby-to-high-level outputDE at 0 V, CL = 15 pF
See Figure 8-10
3300
tPLZOutput disable time from low levelDE at 3 V, CL = 15 pF
See Figure 8-11
13
tPZL1Output enable time to low level10
tPZL2Propagation delay time, standby-to-low-level outputDE at 0 V, CL = 15 pF
See Figure 8-11
3300
All typical values are at 25°C and with a 5-V supply
.tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.