SLLS666F September   2005  – March 2023 SN65HVD50 , SN65HVD51 , SN65HVD52 , SN65HVD53 , SN65HVD54 , SN65HVD55

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Available Options
  6. 6 Pin Configurations
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Recommended Operating Conditions
    3. 7.3 Electrostatic Discharge Protection
    4. 7.4 Driver Electrical Characteristics
    5. 7.5 Driver Switching Characteristics
    6. 7.6 Receiver Electrical Characteristics
    7. 7.7 Receiver Switching Characteristics
    8. 7.8 Thermal Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Device Information
    1. 9.1 Ll-Power Standby Mode
    2. 9.2 Function Tables
    3. 9.3 Equivalent Input and Output Schematic Diagrams
  10. 10Application and Implementation
    1. 10.1 Thermal Characteristics of IC Packages
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4 Driver Electrical Characteristics

over recommended operating conditions unless otherwise noted
PARAMETERTEST CONDITIONSMINTYP(1)MAXUNIT
VI(K)Input clamp voltageII = –18 mA–1.5V
|VOD(SS)|Steady-state differential output voltageIO = 04VCC
RL = 54 Ω, See Figure 8-1 (RS-485)1.72.6
RL = 100 Ω, See Figure 8-1 (RS-422)2.43.2
Vtest = –7 V to 12 V, See Figure 8-21.6
Δ|VOD(SS)|Change in magnitude of steady-state differential output voltage between statesRL = 54 Ω, See Figure 8-1 and Figure 8-2–0.20.2
VOD(RING)Differential Output Voltage overshoot
and undershoot		RL = 54 Ω, CL = 50 pF, See Figure 8-5
See Figure 8-3 for definition		10%(2)
VOC(PP)Peak-to-peak
common-mode
output voltage		HVD50, HVD53See Figure 8-40.5
HVD51, HVD540.4
HVD52, HVD550.4
VOC(SS)Steady-state common-mode
output voltage		See Figure 8-42.23.3
ΔVOC(SS)Change in steady-state common-mode output voltage–0.10.1
IZ(Z) or IY(Z)High-impedance state output currentHVD50, HVD51, HVD52VCC = 0 V, VZ or VY = 12 V,
Other input at 0 V		90μA
VCC = 0 V, VZ or VY = –7 V,
Other input at 0 V		–10
HVD53, HVD54, HVD55VCC = 5 V or 0 V,
DE = 0 V
VZ or VY = 12 V		Other input
at 0 V		90
VCC = 5 V or 0 V,
DE = 0 V
VZ or VY = –7 V		–10
IZ(S) or IY(S)Short-circuit output current(3)VZ or VY = –7 VOther input
at 0 V		–250250mA
VZ or VY = 12 V–250250
IIInput currentD, DE0100μA
C(OD)Differential output capacitanceVOD = 0.4 sin (4E6πt) + 0.5 V,
DE at 0 V		16pF
(1) All typical values are at 25°C and with a 5-V supply.
(2) 10% of the peak-to-peak differential output voltage swing, per TIA/EIA-485
(3) Under some conditions of short-circuit to negative voltages, output currents exceeding the ANSI TIA/EIA-485-A maximum current of 250 mA may occur. Continuous exposure may affect device reliability.