SLLSE94C September 2011 – March 2015 SN65HVD62
PRODUCTION DATA.
If DIRSET1 and DIRSET2 are in a logic High state, the device will be in STANDBY mode. While in STANDBY mode, the Receiver functions normally, detecting carrier frequency activity on the RXIN pin and setting the RXOUT state as discussed below. But the Transmitter circuits are not active in STANDBY, thus the TXOUT pin is idle regardless of the logic state of TXIN. The supply current in STANDBY mode is significantly reduced, allowing power savings when the node is not transmitting.
When not in STANDBY mode, the default power-on state is IDLE. When in IDLE mode, RXOUT is High, and TXOUT is quiet. The device transitions to RECEIVE mode when a valid modulated signal is detected on the RXIN line <OR> the device transitions to TRANSMIT mode when TXIN goes Low. The device stays in either RECEIVE or TRANSMIT mode until DIR Timeout (nominal 16 bit times) after the last activity on RXOUT or TXIN.
When in RECEIVE mode:
When in TRANSMIT mode:
TXIN | [DIRSET1, DIRSET2] | TXOUT | COMMENT |
---|---|---|---|
H | [L,L], [L,H] or [H,L] | < 1 mVPP at 2.176 MHz | Driver not active |
L | VOPP at 2.176 MHz | Driver active | |
X | [H,H] | < 1 mVPP at 2.176 MHz | Standby mode |
RXIN | RXOUT | DIR | COMMENT (see Figure 22) |
---|---|---|---|
IDLE mode (not transmitting or receiving) | |||
< VIT at 2.176 MHz for longer than DIR timeout | H | L | No outgoing or incoming signal |
RECEIVE mode (not already transmitting) | |||
< VIT at 2.176 MHz for less than tDIR Timeout | H | H | Incoming '1' bit, DIR stays HIGH for DIR Timeout |
> VIT at 2.176 MHz for longer than tnoise filter | L | H | Incoming '0' bit, DIR output is HIGH |
TRANSMIT mode (not already receiving) | |||
X | H | L | Outgoing message, DIR stays LOW for DIR Timeout |