SLLSED6B October   2012  – November 2017 SN65HVD82

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Receiver Failsafe
      2. 8.3.2 Low-Power Standby Mode
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Device Configuration
      2. 9.1.2 Bus - Design
      3. 9.1.3 Cable-Length Versus Data Rate
      4. 9.1.4 Stub - Length
      5. 9.1.5 3-V to 5-V Interface
      6. 9.1.6 Noise Immunity
      7. 9.1.7 Transient Protection
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Isolated Bus Node Design
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Design and Layout Considerations For Transient Protection
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Custom Design With WEBENCH® Tools
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Parameter Measurement Information

Input generator rate is 100 kbps, 50% duty cycle, rise and fall times less than 6 nsec, output impedance 50 Ω.

SN65HVD82 s0301-01_llsE11.gif Figure 5. Measurement of Driver Differential Output Voltage With Common-Mode Load
SN65HVD82 s0302-01_llsE11.gif Figure 6. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
SN65HVD82 pmi_dr_sw_llsE11.gif Figure 7. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
SN65HVD82 s0304-01_llsE11.gif
D at 3V to test non-inverting output, D at 0V to test inverting output.
Figure 8. Measurement of Driver Enable and Disable Times With Active High Output and Pull-Down Load
SN65HVD82 s0305-01_llsE11.gif
D at 0V to test non-inverting output, D at 3V to test inverting output.
Figure 9. Measurement of Driver Enable and Disable Times With Active Low Output and Pull-up Load
SN65HVD82 s0306-01_llsE11.gif Figure 10. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
SN65HVD82 s0307-01_llsE11.gif Figure 11. Measurement of Receiver Enable/Disable Times With Driver Enabled
SN65HVD82 s0308-01_llsE11.gif Figure 12. Measurement of Receiver Enable Times With Driver Disabled