SLLS804D March 2009 – August 2016 SN65HVDA540-5-Q1 , SN65HVDA540-Q1 , SN65HVDA541-5-Q1 , SN65HVDA541-Q1 , SN65HVDA542-5-Q1 , SN65HVDA542-Q1
PRODUCTION DATA.
The SN65HVDA54x-Q1 and SN65HVDA54x-5-Q1 devices, known as the HVDA54x and HVDA54x-5 respectively, are designed and qualified for use in automotive applications and meets or exceeds the specifications of the ISO 11898 High Speed CAN (Controller Area Network) Physical Layer standard (transceiver).
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
SN65HVDA54x-Q1, SN65HVDA54x-5-Q1 | SOIC (8) | 4.90 mm × 3.91 mm |
Changes from C Revision (December 2012) to D Revision
Changes from B Revision (September 2010) to C Revision
PIN | TYPE | DESCRIPTION | ||
---|---|---|---|---|
NAME | HVDA54x | HVDA54x-5 | ||
CANH | 7 | 7 | I/O | High level CAN bus line |
CANL | 6 | 6 | I/O | Low level CAN bus line |
GND | 2 | 2 | GND | Ground connection |
NC | — | 5 | Supply | HVDA54x: Transceiver logic level (IO) supply voltage HVDA54x-5: No connect |
RXD | 4 | 4 | O | CAN receive data output (low in dominant bus state, high in recessive bus state) |
STB/S | 8 | 8 | I | Mode select: STB, Standby mode (HVDA540/541) select pin (active high) S, Silent mode (HVDA542) select pin (active high) |
TXD | 1 | 1 | I | CAN transmit data input (low for dominant bus state, high for recessive bus state) |
VCC | 3 | 3 | Supply | Transceiver 5V supply voltage |
VIO | 5 | — | Supply | HVDA54x: Transceiver logic level (IO) supply voltage HVDA54x-5: No connect |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VCC | Supply voltage | –0.3 | 6 | V | |
VIO | I/O supply voltage | –0.3 | 6 | V | |
Voltage at bus terminals (CANH, CANL) | –27 | 40 | V | ||
IO | Receiver output current (RXD) | 20 | mA | ||
VI | Voltage input (TXD, STB, S) | HVDA54x | –0.3 | 6 V and VI ≤ VIO + 0.3 | V |
HVDA54x-5 | –0.3 | 6 | V | ||
TJ | Operating virtual-junction temperature | –40 | 150 | °C | |
TLEAD | Lead temperature (soldering, 10 seconds) | 260 | °C | ||
Tstg | Storage temperature | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002(1) | All pins except 6 and 7 | ±4000 | V |
Pins 6 and 7(2) | ±12000 | ||||
Charged-device model (CDM), per AEC Q100-011 | ±1000 | ||||
Machine model | ±7000 | ||||
IEC 61000-4-2 contact discharge(3) | Pins 6 and 7 to pin 2 | ±7000 |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VCC | Supply voltage | 4.68 | 5.33 | V | |
VIO | I/O supply voltage | 3 | 5.33 | V | |
VI or VIC | Voltage at any bus terminal (separately or common mode) | –12 | 12 | V | |
VIH | High-level input voltage | TXD, STB, S (for HVD54x-5: VIO = VCC) | 0.7 × VIO | VIO | V |
VIL | Low-level input voltage | TXD, STB, S (for HVD54x-5: VIO = VCC) | 0 | 0.3 × VIO | V |
VID | Differential input voltage, bus | Between CANH and CANL | –6 | 6 | V |
IOH | High-level output current | RXD | –2 | mA | |
IOL | Low-level output current | RXD | 2 | mA | |
TA | Operating ambient free-air temperature | See Thermal Information and Power Dissipation Ratings | –40 | 125 | °C |
THERMAL METRIC(1) | HVDA54x, HVDA54x-5-Q1 | UNIT | ||
---|---|---|---|---|
D (SOIC) | ||||
8 PINS | ||||
RθJA | Junction-to-ambient thermal resistance | Low-K thermal resistance | 140 | °C/W |
High-K thermal resistance | 112 | |||
RθJC(top) | Junction-to-case (top) thermal resistance | 56 | °C/W | |
RθJB | Junction-to-board thermal resistance | 50 | °C/W | |
ψJT | Junction-to-top characterization parameter | 13 | °C/W | |
ψJB | Junction-to-board characterization parameter | 55 | °C/W | |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | — | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
SUPPLY CHARACTERISTICS (HVDA54x) | |||||||
ICC | 5-V supply current | Standby mode (HVDA540/541 Only) | STB at VIO, VCC = 5.33 V, VIO = 3 V, TXD at VIO (2) | 5 | µA | ||
Normal mode (Dominant) | TXD at 0 V, 60-Ω load, STB / S at 0 V | 50 | 70 | mA | |||
Normal mode (Recessive) | TXD at VIO, No load, STB / S at 0 V or S at VIO | 5.5 | 10 | ||||
Silent Mode (HVDA542 only) | TXD at VIO, No load, STB / S at 0 V or S at VIO | 5.5 | 10 | ||||
IIO | I/O supply current | Standby mode (HVDA540/541 Only) | STB at VIO , VCC = 5.33 V or 0 V, RXD floating, TXD at VIO
TA = –40°C, 25°C, 125°C(3) |
7 | 15 | µA | |
Normal mode (recessive or dominant) and Silent Mode (HVDA542 Only) | VCC = 5.33 V, RXD floating, TXD at 0 V or VIO. Normal Mode: STB or S at 0 V. Silent Mode (HVDA542): S at VIO. | 75 | 300 | ||||
UVVCC | Undervoltage detection on VCC for forced standby mode | 3.2 | 3.6 | 4 | V | ||
VHYS(UVVCC) | Hysteresis voltage for undervoltage detection on UVVCC for standby mode | 200 | mV | ||||
UVVIO | Undervoltage detection on VIO for forced standby mode | 1.9 | 2.45 | 2.95 | V | ||
VHYS(UVVIO) | Hysteresis voltage for undervoltage detection on UVVIO for forced standby mode | 130 | mV | ||||
SUPPLY CHARACTERISTICS (HVDA54x-5) | |||||||
ICC | 5-V supply current | Standby mode (HVDA540-5/541-5 Only) | STB at VCC, VCC = 5.33 V, TXD at VCC (2) | 20 | µA | ||
Normal mode (Dominant) | TXD at 0 V, 60-Ω load, STB / S at 0 V | 50 | 70 | mA | |||
Normal mode (Recessive) | TXD at VIO, No load, STB / S at 0 V or S at VIO | 5.5 | 10 | ||||
Silent Mode (HVDA542 only) | TXD at VIO, No load, STB / S at 0 V or S at VIO | 5.5 | 10 | ||||
UVVCC | Undervoltage detection on VCC for forced standby mode | 3.2 | 3.6 | 4 | V | ||
VHYS(UVVCC) | Hysteresis voltage for undervoltage detection on UVVCC for standby mode | 240 | mV | ||||
DEVICE SWITCHING CHARACTERISTICS: PROPAGATION TIME (LOOP TIME TXD TO RXD) | |||||||
tPROP(LOOP1) | Total loop delay, driver input (TXD) to receiver output (RXD), recessive to dominant | Figure 9, STB at 0 V | 70 | 230 | ns | ||
tPROP(LOOP2) | Total loop delay, driver input (TXD) to receiver output (RXD), dominant to recessive | 70 | 230 | ||||
DRIVER ELECTRICAL CHARACTERISTICS | |||||||
VO(D) | Bus output voltage (dominant) | CANH | VI = 0 V, STB / S at 0 V, RL = 60 Ω, See Figure 2 and Figure 15 |
2.9 | 4.5 | V | |
CANL | 0.8 | 1.75 | |||||
VO(R) | Bus output voltage (recessive) | VI = VIO, VIO = 3 V, STB at 0 V or S at X(4), RL = 60 Ω, See Figure 2 and Figure 15 | 2 | 2.5 | 3 | V | |
VO(STBY) | Bus output voltage, standby mode (HVDA540, HVDA541 only) | STB / S at VIO, RL = 60 Ω, See Figure 2 and Figure 15 |
–0.1 | 0.1 | V | ||
VOD(D) | Differential output voltage (dominant) | VI = 0 V, RL = 60 Ω, STB / S at 0 V, See Figure 2, Figure 15, and Figure 3 |
1.5 | 3 | V | ||
VI = 0 V, RL = 45 Ω, STB / S at 0 V, See Figure 2, Figure 15, and Figure 3 |
1.4 | 3 | |||||
VOD(R) | Differential output voltage (recessive) | VI = 3 V, STB / S at 0 V, RL = 60 Ω, See Figure 2 and Figure 15 | –0.012 | 0.012 | V | ||
VI = 3 V, STB / S at 0 V, No load | –0.5 | 0.05 | |||||
VSYM | Output symmetry (dominant or recessive) (VO(CANH) + VO(CANL)) | STB / S at 0 V, RL = 60 Ω, See Figure 12 |
0.9 VCC | VCC | 1.1 VCC | V | |
VOC(SS) | Steady-state common-mode output voltage | STB / S at 0 V, RL = 60 Ω, See Figure 8 |
2 | 2.5 | 3 | V | |
ΔVOC(SS) | Change in steady-state common-mode output voltage | STB / S at 0 V, RL = 60 Ω, See Figure 8 |
40 | mV | |||
IOS(SS)_DOM | Short-circuit steady-state output current, Dominant | VCANH = 0 V, CANL open, TXD = low, See Figure 11 |
–100 | mA | |||
VCANL = 32 V, CANH open, TXD = low, See Figure 11 | 100 | ||||||
IOS(SS)_REC | Short-circuit steady-state output current, Recessive | –20 V ≤ VCANH ≤ 32 V, CANL open, TXD = high, See Figure 11 |
–10 | 10 | mA | ||
–20 V ≤ VCANL ≤ 32 V, CANH open, TXD = high, See Figure 11 |
–10 | 10 | |||||
CO | Output capacitance | See receiver input capacitance | |||||
DRIVER SWITCHING CHARACTERISTICS | |||||||
tPLH | Propagation delay time, low-to-high level output | STB / S at 0 V, See Figure 4 | 65 | ns | |||
tPHL | Propagation delay time, high-to-low level output | STB / S at 0 V, See Figure 4 | 50 | ns | |||
tR | Differential output signal rise time | STB / S at 0 V, See Figure 4 | 25 | ns | |||
tF | Differential output signal fall time | STB / S at 0 V, See Figure 4 | 55 | ns | |||
tEN | Enable time from standby or silent mode to normal mode dominant | See Figure 7 | 20 | µs | |||
t(DOM)(5) | Dominant time out | See Figure 10 | 300 | 400 | 700 | µs | |
RECEIVER ELECTRICAL CHARACTERISTICS | |||||||
VIT+ | Positive-going input threshold voltage, normal mode | STB / S at 0 V, See Table 1 | 800 | 900 | mV | ||
VIT– | Negative-going input threshold voltage, normal mode | STB / S at 0 V, See Table 1 | 500 | 650 | mV | ||
Vhys | Hysteresis voltage (VIT+ – VIT–) | 100 | 125 | mV | |||
VIT(STBY) | Input threshold voltage, standby mode (HVDA541 only) | STB at VIO | 400 | 1150 | mV | ||
II(OFF_LKG) | Power-off (unpowered) bus input leakage current | CANH = CANL = 5 V, VCC at 0 V, VIO at 0 V, TXD at 0 V |
3 | µA | |||
CI | Input capacitance to ground (CANH or CANL) | HVDA54x: TXD at VIO, VIO at 3.3 V. HVDA54x-5: TXD at VCC VI = 0.4 sin (4E6πt) + 2.5 V |
13 | pF | |||
CID | Differential input capacitance | HVDA54x: TXD at VIO, VIO at 3.3 V. HVDA54x-5: TXD at VCC VI = 0.4 sin(4E6πt) |
5 | pF | |||
RID | Differential input resistance | HVDA54x: TXD at VIO, VIO = 3.3 V, STB at 0 V HVDA54x-5: TXD at VCC, STB at 0 V |
29 | 80 | kΩ | ||
RIN | Input resistance (CANH or CANL) | 14.5 | 25 | 40 | kΩ | ||
RI(M) | Input resistance matching [1 – ®IN(CANH)/RIN(CANL))] × 100% |
V(CANH) = V(CANL) | –3 | 0 | 3 | % | |
RECEIVER SWITCHING CHARACTERISTICS | |||||||
tPLH | Propagation delay time, low-to-high-level output | STB / S at 0 V , See Figure 6 | 95 | ns | |||
tPHL | Propagation delay time, high-to-low-level output | STB / S at 0 V , See Figure 6 | 60 | ns | |||
tR | Output signal rise time | STB / S at 0 V , See Figure 6 | 13 | ns | |||
tF | Output signal fall time | STB / S at 0 V , See Figure 6 | 10 | ns | |||
tBUS | Dominant time required on bus for wake-up from standby (HVDA541 only) | STB at VIO, See Figure 17 and Figure 18 | 1.5 | 5 | µs | ||
tCLEAR | Recessive time on the bus to clear the standby mode receiver output (RXD) if standby mode is entered while bus is dominant (HVDA541 only) | 1.5 | 5 | µs | |||
TXD PIN CHARACTERISTICS | |||||||
VIH | High-level input voltage | HVD54x-5: VIO = VCC | 0.7 × VIO | V | |||
VIL | Low-level input voltage | HVD54x-5: VIO = VCC | 0.3 × VIO | V | |||
IIH | High-level input current | HVDA54x: TXD at VIO HVDA54x-5: TXD at VCC | –2 | 2 | µA | ||
IIL | Low-level input current | TXD at 0 V | –100 | –7 | µA | ||
RXD PIN CHARACTERISTICS | |||||||
VOH | High-level output voltage | IO = –2 mA, See Figure 6 HVD54x-5: VIO = VCC |
0.8 × VIO | V | |||
VOL | Low-level output voltage | IO = 2 mA, See Figure 6 HVD54x-5: VIO = VCC |
0.2 × VIO | V | |||
STB PIN CHARACTERISTICS (HVDA540 AND HVDA541 ONLY) | |||||||
VIH | High-level input voltage | HVD54x-5: VIO = VCC | 0.7 × VIO | V | |||
VIL | Low-level input voltage | HVD54x-5: VIO = VCC | 0.3 × VIO | V | |||
IIH | High-level input current | HVDA54x: STB at VIO HVDA54x-5: STB at VCC | –2 | 2 | µA | ||
IIL | Low-level input current | STB at 0 V | –20 | µA | |||
S PIN CHARACTERISTICS (HVDA542 ONLY) | |||||||
VIH | High-level input voltage | HVD54x-5: VIO = VCC | 0.7 × VIO | V | |||
VIL | Low-level input voltage | HVD54x-5: VIO = VCC | 0.3 × VIO | V | |||
IIH | High-level input current | HVDA54x: S at VIO HVDA54x-5: S at VCC | 30 | µA | |||
IIL | Low-level input current | S at 0 V | –2 | 2 | µA | ||
Thermal shutdown temperature | 185 | °C |
MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|
PD | Average power dissipation | VCC = 5 V, VIO = VCC, TJ = 27°C, RL = 60 Ω, STB at 0 V, Input to TXD at 500 kHz, 50% duty cycle square wave, CL at RXD = 15 pF |
140 | mW | ||
VCC = 5.33 V, VIO = VCC, TJ = 130°C, RL = 60 Ω, STB at 0 V, Input to TXD at 500 kHz, 50% duty cycle square wave, CL at RXD = 15 pF |
215 |
STB = 0 V RL= 60 Ω CL= Open Rcm= open Temp = 25°C | ||
INPUT | OUTPUT | |||
---|---|---|---|---|
VCANH | VCANL | |VID| | R | |
–11.1 V | –12 V | 900 mV | L | VOL |
12 V | 11.1 V | 900 mV | L | |
–6 V | –12 V | 6 V | L | |
12 V | 6 V | 6 V | L | |
–11.5 V | –12 V | 500 mV | H | VOH |
12 V | 11.5 V | 500 mV | H | |
–12 V | –6 V | 6 V | H | |
6 V | 12 V | 6 V | H | |
Open | Open | X | H |
The device meets or exceeds the specifications of the ISO 11898 High Speed CAN (Controller Area Network) Physical Layer standard (transceiver). This device provides CAN transceiver functions: differential transmit capability to the bus and differential receive capability at data rates up to 1 megabit per second (Mbps). The device includes many protection features providing device and CAN network robustness.
The HVDA54x devices have an I/O supply voltage input pin (VIO) to ratiometrically level shift the digital logic input and output levels with respect to VIO for compatibility with protocol controllers having I/O supply voltages between 3 V and 5.33 V.
The HVDA54x-5 devices have a single VCC supply (5 V). The digital logic input and output levels for these devices are with respect to VCC for compatibility with protocol controllers having I/O supply voltages between 4.68 V and 5.33 V.
During normal mode, the only mode where the CAN driver is active, the TXD dominant time out circuit prevents the transceiver from blocking network communication in event of a hardware or software failure where TXD is held dominant longer than the time-out period t(DOM). The dominant time out circuit is triggered by a falling edge on TXD. If no rising edge is seen before the time out constant of the circuit expires (t(DOM)) the CAN bus driver is disabled freeing the bus for communication between other network nodes. The CAN driver is reactivated when a recessive signal is seen on TXD pin, thus clearing the dominant state time out. The CAN bus pins is biased to recessive level during a TXD dominant state time out.
NOTE
The maximum dominant TXD time allowed by the TXD Dominant state time out limits the minimum possible data rate of the device. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the t(DOM) minimum, limits the minimum bit rate.
The minimum bit rate may be calculated in Equation 1:
If the junction temperature of the device exceeds the thermal shut down threshold the device will turn off the CAN driver circuits. This condition is cleared once the temperature drops below the thermal shut down temperature of the device. The CAN bus pins will be biased to recessive level during a thermal shutdown.
Both of the supply pins have undervoltage detection which place the device in forced standby mode to protect the bus during an undervoltage event on either the VCC or VIO supply pins. If VIO is undervoltage the RXD pin is tri-stated and the device does not pass any wake-up signals from the bus to the RXD pin. Since the device is placed into forced standby mode the CAN bus pins have a common mode bias to ground protecting the CAN network, see Figure 15 and Figure 16.
The device is designed to be an ideal passive load to the CAN bus if it is unpowered. The bus pins (CANH, CANL) have extremely low leakage currents when the device is unpowered so they will not load down the bus but rather be no load. This is critical, especially if some nodes of the network will be unpowered while the rest of the network remains in operation.
NOTE
Once an undervoltage condition is cleared and the VCC and VIO have returned to valid levels the device will typically need 300 µs to transition to normal operation.
DEVICE | VCC | VIO | DEVICE STATE | BUS | RXD |
---|---|---|---|---|---|
HVDA540 | Bad | Good | Forced Standby Mode | Common mode bias to GND(1) | HIGH (Recessive) |
HVDA541 | Forced Standby Mode | Common mode bias to GND(1) | Mirrors bus state via wake-up filter(3) | ||
HVDA542 | Forced Standby Mode | Common mode bias to GND(1) | HIGH (Recessive) | ||
HVDA54x | Good | Bad | Forced Standby Mode(2) | Common mode bias to GND(1) | tri-state |
HVDA54x-5 | Bad | N/A | Forced Standby Mode | Common mode bias to GND(1) | HIGH (Recessive) or tri-state |
All Devices | Unpowered | Unpowered | No Load | High Z |
The device has integrated pullup and pulldowns on critical pins to place the device into known states if the pins float. The TXD pin is pulled up to VIO to force a recessive input level if the pin floats. The STB is pulled up to the IO supply pin, VIO(HVDA540 and HVDA541), or VCC (HVDA540-5 and HVDA541-5) to force the device in standby mode (low power) if the pin floats. The S pin is pulled down to GND to force the device into normal mode if the pin floats (HVDA542 and HVDA542-5).
The device has several protection features that limit the short circuit current when a CAN bus line is shorted. These include CAN driver current limiting (dominant and recessive) and TXD dominant state time out to prevent continuously driving dominant. During CAN communication the bus switches between dominant and recessive states, thus the short circuit current may be viewed either as the current during each bus state or as a DC average current. For system current and power considerations in termination resistance and common mode choke ratings the average short circuit current should be used. The device has TXD dominant state time out which prevents permanently having the higher short circuit current of dominant state. The CAN protocol also has forced state changes and recessive bits such as bit stuffing, control fields, and interframe space. These ensure there is a minimum recessive amount of time on the bus even if the data field contains a high percentage of dominant bits.
NOTE
The short circuit current of the bus depends on the ratio of recessive to dominant bits and their respective short circuit currents.
The average short circuit current may be calculated by Equation 2:
where
The device has two main operating modes: normal mode (all devices) and standby mode (HVDA540 / 541) or silent mode (HVDA542). Operating mode selection is made through the STB (HVDA540 / 541) or the S (HVDA542) input pin.
DEVICE | STB / S | MODE | DRIVER | RECEIVER | RXD Pin |
---|---|---|---|---|---|
All Devices | LOW | Normal Mode | Enabled (On) | Enabled (On) | Mirrors bus state(1) |
HVDA540 | HIGH | Standby Mode (No Wake Up) | Disabled (Off) | Disabled (Off) | Recessive (HIGH) |
HVDA541 | HIGH | Standby Mode (RXD Wake Up Request) | Disabled (Off) | Low power wake-up receiver and bus monitor enabled | Mirrors bus state via wake-up filter(2) |
HVDA542 | HIGH | Silent Mode | Disabled (Off) | Enabled (On) | Mirrors bus state(1) |
The CAN bus has three valid states during powered operation depending on the mode of the device. In normal mode the bus may be dominant (logic LOW) where the bus lines are driven differentially apart or recessive (logic HIGH) where the bus lines are biased to VCC/2 via the high-ohmic internal input resistors RIN of the receiver. The third state is low power standby mode where the bus lines will be biased to GND via the high-ohmic internal input resistors RIN of the receiver.
This is the normal operating mode of the device. It is selected by setting STB or S low. The CAN driver and receiver are fully operational and CAN communication is bidirectional. The driver is translating a digital input on TXD to a differential output on CANH and CANL. The receiver is translating the differential signal from CANH and CANL to a digital output on RXD. In recessive state the CAN bus pins (CANH and CANL) are biased to
0.5 × VCC. In dominant state the bus pins are driven differentially apart. Logic high is equivalent to recessive on the bus and logic low is equivalent to a dominant (differential) signal on the bus.
This is the low power mode of the device. It is selected by setting STB high. The CAN driver and receiver are turned off and bidirectional CAN communication is not possible. There is no wake up capability in the HVDA540, the RXD pin will remain recessive (high) while the device is in standby mode. This state is supplied via the VIO supply, thus the VCC (5V) supply may be turned off for additional power savings at the system level. The local protocol controller (MCU) should reactivate the device to normal mode to enable communication via the CAN bus. The 5 V (VCC) supply needs to be reactivated by the local protocol controller to resume normal mode if it has been turned off for low-power standby operation. The CAN bus pins are weakly pulled to GND, see Figure 15 and Figure 16.
This is the low power mode of the device. It is selected by setting STB high. The CAN driver and main receiver are turned off and bidirectional CAN communication is not possible. The low power receiver and bus monitor, both supplied via the VIO supply, are enabled to allow for RXD wake up requests via the CAN bus. The VCC (5V) supply may be turned off for additional power savings at the system level. A wake up request will be output to RXD (driven low) for any dominant bus transmissions longer than the filter time tBUS. The local protocol controller (MCU) should monitor RXD for transitions and then reactivate the device to normal mode based on the wake up request. The 5 V (VCC) supply needs to be reactivated by the local protocol controller to resume normal mode if it has been turned off for low-power standby operation. The CAN bus pins are weakly pulled to GND, see Figure 15 and Figure 16.
If the bus has a fault condition where it is stuck dominant while the HVDA541 is placed into standby mode via the STB pin, the device locks out the RXD wake up request until the fault has been removed to prevent false wake up signals in the system.
This is the silent (receive only) mode of the device. It is selected by setting S high. The CAN driver is turned off while the receiver remains active and RXD will output the received bus state. There is no low power mode in the HVDA542 except for VCC and VIO supply undervoltage conditions (see Undervoltage Lockout and Unpowered Device).
INPUTS | OUTPUTS | DRIVEN BUS STATE | |||
---|---|---|---|---|---|
DEVICE | STB / S(1) | TXD(1) | CANH(1) | CANL(1) | |
All Devices | L | L | H | L | Dominant |
L | H | Z | Z | Recessive | |
L | Open | Z | Z | Recessive | |
HVDA540/541(2) | H | X | Y | Y | Recessive |
HVDA542(3) | H | X | Z | Z | Recessive |
DEVICE MODE | CAN DIFFERENTIAL INPUTS VID = V(CANH) – V(CANL) |
BUS STATE | RXD PIN(1) | |
---|---|---|---|---|
STANDBY (HVDA540)(2) | X | X | H | |
STANDBY WITH RXD WAKE UP REQUEST (HVDA541)(3) | VID ≥ 1.15 V | DOMINANT | L | |
0.4 V < VID < 1.15 V | ? | ? | ||
VID ≤ 0.4 V | RECESSIVE | H | ||
NORMAL OR SILENT | VID ≥ 0.9 V | DOMINANT | L | |
0.5 V < VID < 0.9 V | ? | ? | ||
VID ≤ 0.5 V | RECESSIVE | H | ||
ANY | Open | N/A | H |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
These CAN transceivers are typically used in applications with a host microprocessor or FPGA that includes the data link layer portion of the CAN protocol. Below are typical application configurations for both 5-V and 3.3-V microprocessor applications. The bus termination is shown for illustrative purposes.
The ISO 11898-2 Standard specifies a maximum bus length of 40 m and maximum stub length of 0.3 m. However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a bus. A large number of nodes requires transceivers with high input impedance such as the HVDA54x family of transceivers.
Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO 11898-2. They have made system-level tradeoffs for data rate, cable length, and parasitic loading of the bus. Examples of some of these specifications are ARINC825, CANopen, DeviceNet, and NMEA2000.
The ISO 11898 standard specifies the interconnect to be a twisted pair cable (shielded or unshielded) with
120-Ω characteristic impedance (ZO). Resistors equal to the characteristic impedance of the line should be used to terminate both ends of the cable to prevent signal reflections. Unterminated drop lines (stubs) connecting nodes to the bus should be kept as short as possible to minimize signal reflections. The termination may be on the cable or in a node, but if nodes may be removed from the bus, the termination must be carefully placed so that two terminations always exist on the network. Termination may be a single 120-Ω resistor at the end of the bus, either on the cable or in a terminating node. If filtering and stabilization of the common mode voltage of the bus is desired, then split termination may be used (see Figure 21). Split termination improves the electromagnetic emissions behavior of the network by eliminating fluctuations in the bus common-mode voltages at the start and end of message transmissions.
The family of transceivers have variants for both 5-V only applications and applications where level shifting is needed for a 3.3-V micrcontroller.
Transceiver loop delay is a measure of the overall device propagation delay and consists of the delay from driver input (TXD pin) to differential outputs (CANH and CANL), plus the delay from the receiver inputs (CANH and CANL) to the output pin RXD.
In Figure 22 is displayed the loop delay at 1 Mbps with Vio equal to 3.3 V
Figure 25, Figure 26, and Figure 27 show three different example applications using the HVDA54x family of transceivers. Different devices and configurations can be used depending on the I/O voltage levels supported by the MCU and different operating modes required by the end application.
To ensure reliable operation at all data rates and supply voltages, each supply should be decoupled with a
100-nF ceramic capacitor located as close to the VCC supply pins as possible. Either a linear regulator or switched-mode power supply may be used. Power and ground nets should be routed on the PCB using planes or wide traces so that series resistance and inductance are minimized.
Robust and reliable bus node design often requires the use of external transient protection device to protect against EFT and surge transients that may occur in industrial enviroments. Because ESD and transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high-frequency layout techniques must be applied during PCB design. The HVDA54x-Q1 and HVDA54x-5-Q1 families come with high on-chip IEC ESD protection, but if higher levels of system level immunity are desired external TVS diodes can be used. TVS diodes and bus filtering capacitors should be placed as close to the onboard connectors as possible to prevent noisy transient events from propagating further into the PCB and system.
NOTE
High-frequency currents follows the path of least impedance and not the path of least resistance.