SLLS804D March   2009  – August 2016 SN65HVDA540-5-Q1 , SN65HVDA540-Q1 , SN65HVDA541-5-Q1 , SN65HVDA541-Q1 , SN65HVDA542-5-Q1 , SN65HVDA542-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Power Dissipation Ratings
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Digital Inputs and Outputs
      2. 8.3.2 TXD Dominant State Time Out
      3. 8.3.3 Thermal Shutdown
      4. 8.3.4 Undervoltage Lockout and Unpowered Device
      5. 8.3.5 Floating Pins
      6. 8.3.6 CAN Bus Short-Circuit Current Limiting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Bus States by Mode
      2. 8.4.2 Normal Mode
      3. 8.4.3 Standby Mode (HVDA540)
      4. 8.4.4 Standby Mode With RXD Wake Up-Request (HVDA541)
        1. 8.4.4.1 RXD Wake Up Request Lock Out for Bus Stuck Dominant Fault (HVDA541)
      5. 8.4.5 Silent (Receive Only) Mode (HVDA542)
      6. 8.4.6 Driver and Receiver Function Tables
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 3.3-V I/O Voltage Level and Normal Mode
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Loop Propagation Delay
        3. 9.2.1.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

HVDA54x D Package
8-Pin SOIC
Top View
HVDA54x-5 D Package
8-Pin SOIC
Top View

Pin Functions

PIN TYPE DESCRIPTION
NAME HVDA54x HVDA54x-5
CANH 7 7 I/O High level CAN bus line
CANL 6 6 I/O Low level CAN bus line
GND 2 2 GND Ground connection
NC — 5 Supply HVDA54x: Transceiver logic level (IO) supply voltage
HVDA54x-5: No connect
RXD 4 4 O CAN receive data output (low in dominant bus state, high in recessive bus state)
STB/S 8 8 I Mode select:
STB, Standby mode (HVDA540/541) select pin (active high)
S, Silent mode (HVDA542) select pin (active high)
TXD 1 1 I CAN transmit data input (low for dominant bus state, high for recessive bus state)
VCC 3 3 Supply Transceiver 5V supply voltage
VIO 5 — Supply HVDA54x: Transceiver logic level (IO) supply voltage
HVDA54x-5: No connect