The SN65HVS885 is an eight channel, digital-input serializer for high-channel density digital input modules in industrial and building automation. Operating from a 5-V supply the device accepts field input voltages of up to 34 V. In combination with galvanic isolators the device completes the interface between the high voltage signals on the field-side and the low-voltage signals on the controller side. Inputs signals are current limited and then validated by internal debounce filters.
With the addition of few external components, the input switching characteristic can be configured in accordance with IEC61131-2 for Type 1, 2 and 3 sensor switches.
Upon the application of load and clock signals, input data is latched in parallel into the shift register and afterwards clocked out serially.
Cascading of multiple devices is possible by connecting the serial output of the leading device with the serial input of the following device, enabling the design of high-channel count input modules. Multiple devices can be cascaded through a single serial port, reducing both the isolation channels and controller inputs required.
Input status can be visually indicated via constant current LED outputs. The current limit on the inputs is set by a single, external, precision resistor. An on-chip temperature sensor provides diagnostic information for graceful shutdown and system safety.
The SN65HVS885 is available in a 28-pin PWP PowerPAD™ package, allowing for efficient heat dissipation. The device is specified for operation at temperatures from –40°C to 125°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
SN65HVS885 | HTSSOP (28) | 9.70 mm × 4.40 mm |
Changes from * Revision (January 2009) to A Revision
PIN | DESCRIPTION | |
---|---|---|
NAME | NO. | |
CE | 24 | Clock Enable Input |
CLK | 25 | Serial Clock Input |
DB0 | 1 | Debounce select inputs |
DB1 | 2 | |
GND | 28 | Device Ground |
HOT | 16 | Over-Temperature Flag |
IPx | 3, 5, 7, 9, 11, 18, 20, 22 |
Input Channel x |
LD | 26 | Load Pulse Input |
NC | 14 | Not Connected |
REx | 4, 6, 8, 10, 12, 17, 19, 21 |
Return Path x (LED drive) |
RLIM | 13 | Current Limiting Resistor |
SIP | 27 | Serial Data Input |
SOP | 23 | Serial Data Output |
VCC | 15 | 5 V Device Supply |
MIN | MAX | UNIT | ||||
---|---|---|---|---|---|---|
VCC | Device power input | VCC | –0.5 | 6 | V | |
VIPx | Field digital inputs | IPx | –0.3 | 36 | V | |
VID | Voltage at any logic input | DB0, DB1, CLK, SIP, CE, LD | –0.5 | 6 | V | |
IO | Output current | HOT, SOP | –8 | 8 | mA | |
PTOT | Continuous total power dissipation | See Thermal Information | ||||
TJ | Junction temperature | 170 | °C | |||
Tstg | Storage temperature | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | All pins | ±4000 | V |
IPx | ±15000 | ||||
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 | ||||
Machine model (MM)(3) | ±100 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VCC | Device supply voltage | 4.5 | 5 | 5.5 | V |
VIPL | Field input low-state input voltage | 0 | 4 | V | |
VIPH | Field input high-state input voltage | 5.5 | 34 | V | |
VIL | Logic low-state input voltage | 0 | 0.8 | V | |
VIH | Logic high-state input voltage | 2.0 | 5.5 | V | |
RLIM | Current limiter resistor | 17 | 25 | 500 | kΩ |
fIP (1) | Input data rate | 0 | 1 | Mbps | |
TA | Device | –40 | 125 | °C | |
TJ | Junction Temperature | 150 | °C |
THERMAL METRIC(1) | SN65HVS885 | UNIT | |||
---|---|---|---|---|---|
PWP (HTSSOP) | |||||
28 PINS | |||||
RθJA | Junction-to-ambient thermal resistance | High-K thermal resistance | 35 | °C/W | |
RθJC(top) | Junction-to-case (top) thermal resistance | 4.27 | °C/W | ||
RθJB | Junction-to-board thermal resistance | 15 | °C/W | ||
ψJT | Junction-to-top characterization parameter | 0.6 | °C/W | ||
ψJB | Junction-to-board characterization parameter | 15.9 | °C/W | ||
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 2.4 | °C/W |
PARAMETER | TERMINAL | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|---|
FIELD INPUTS | ||||||||
VTH–(IP) | Low-level device input threshold voltage | IP0–IP7 | RLIM = 25 kΩ | 4 | 4.3 | V | ||
VTH+(IP) | High-level device input threshold voltage | 5.2 | 5.5 | V | ||||
VHYS(IP) | Device input hysteresis | 0.9 | V | |||||
VTH–(IN) | Low-level field input threshold voltage | Measured at field side of RIN |
4.5 V < VCC < 5.5 V, RIN = 1.2 kΩ ± 5%, RLIM = 25 kΩ, TA ≤ 125°C |
6 | 8.4 | V | ||
VTH+(IN) | High-level field input threshold voltage | 9.4 | 10 | V | ||||
VHYS(IN) | Field input hysteresis | 1 | V | |||||
RIP | Input resistance | IP0–IP7 | 3 V < VIPx < 6 V, RLIM = 25 kΩ |
0.2 | 0.63 | 1.1 | kΩ | |
IIP-LIM | Input current limit | IP0–IP7 | RLIM = 25 kΩ | 3.15 | 3.6 | 4 | mA | |
tDB | Debounce times of input channels | IP0–IP7 | DB0 = open, DB1 = GND | 0 | ms | |||
DB0 = GND, DB1 = open | 1 | |||||||
DB0 = DB1 = open | 3 | |||||||
IRE-on | RE on-state current | RE0–RE7 | RLIM = 25 kΩ, REX = GND | 2.8 | 3.15 | 3.5 | mA | |
DEVICE SUPPLY | ||||||||
ICC(VCC) | Supply current | VCC | IP0 to IP7 = 24V, REX = GND, All logic inputs open |
6.5 | 10 | mA | ||
LOGIC INPUTS AND OUTPUTS | ||||||||
VOL | Logic low-level output voltage | SOP, HOT | IOL = 20 μA | 0.4 | V | |||
VOH | Logic high-level output voltage | IOH = –20 μA | 4 | V | ||||
IIL | Logic input leakage current | DB0, DB1, SIP, LD, CE, CLK |
–50 | 50 | μA | |||
TOVER | Over-temperature indication | 150 | °C | |||||
TSHDN | Shutdown temperature | 170 | °C | |||||
POWER DISSIPATION | ||||||||
PD | Power Dissipation | VCC = 5 V, RIN = 0Ω, RLIM = 25 kΩ, RE0 – RE7 = GND, fCLK = 100 MHz |
IP0-IP7 = 34 V | 1100 | mW | |||
IP0-IP7 = 24 V | ||||||||
IP0-IP7 = 20 V | ||||||||
IP0-IP7 = 12 V |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
tW1 | CLK pulse width | See Figure 6 | 4 | ns | ||
tW2 | LD pulse width | See Figure 4 | 6 | ns | ||
tSU1 | SIP to CLK setup time | See Figure 7 | 4 | ns | ||
tH1 | SIP to CLK hold time | See Figure 7 | 2 | ns | ||
tSU2 | Falling edge to rising edge (CE to CLK) setup time | See Figure 8 | 4 | ns | ||
tREC | LD to CLK recovery time | See Figure 5 | 2 | ns | ||
fCLK | Clock pulse frequency | See Figure 6 | DC | 100 | MHz |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tPLH1, tPHL1 | CLK to SOP | CL = 15 pF, see Figure 6 | 10 | ns | ||
tPLH2, tPHL2 | LD to SOP | CL = 15 pF, see Figure 4 | 14 | ns | ||
tr, tf | Rise and fall times | CL = 15 pF, see Figure 6 | 6 | ns |
For the complete serial interface timing, refer to Figure 17.