SLLS236J October   1996  – July 2024 SN65LBC184 , SN75LBC184

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: Driver
    6. 5.6  Electrical Characteristics: Receiver
    7. 5.7  Driver Switching Characteristics
    8. 5.8  Receiver Switching Characteristics
    9. 5.9  Dissipation Ratings
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Data Rate and Bus Length
        2. 8.2.1.2 Stub Length
        3. 8.2.1.3 Bus Loading
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 SN65LBC184 Test Description
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.1 SN65LBC184 Test Description

The SN65LBC184 is tested against the IEC 61000-4-5 recommended transient identified as the combination wave. The combination wave provides a 1.2-/50μs open-circuit voltage waveform and a 8-/20μs short-circuit current waveform shown in Figure 8-4. The testing is performed with a combination/hybrid pulse generator with an effective output impedance of 2Ω. The setup for the overvoltage stress is shown in Figure 8-5 with all testing performed with power applied to the SN65LBC184 circuit.

SN65LBC184 SN75LBC184 Open-Circuit Voltage and Short-Circuit Current WaveformsFigure 8-4 Open-Circuit Voltage and Short-Circuit Current Waveforms

The SN65LBC184 is tested and evaluated for both maximum (single pulse) as well as life test (multiple pulse) capabilities. The SN65LBC184 is evaluated against transients of both positive and negative polarity and all testing is performed with the worst-case transient polarity. Transient pulses are applied to the bus pins (A and B) across ground as shown in Figure 8-5.

SN65LBC184 SN75LBC184 Overvoltage Stress Test CircuitFigure 8-5 Overvoltage Stress Test Circuit