SLLS236J October   1996  – July 2024 SN65LBC184 , SN75LBC184

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: Driver
    6. 5.6  Electrical Characteristics: Receiver
    7. 5.7  Driver Switching Characteristics
    8. 5.8  Receiver Switching Characteristics
    9. 5.9  Dissipation Ratings
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Data Rate and Bus Length
        2. 8.2.1.2 Stub Length
        3. 8.2.1.3 Bus Loading
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 SN65LBC184 Test Description
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4 Device Functional Modes

When the driver enable pin (DE) is logic high, the differential outputs A and B follow the logic states at data input D. A logic high at D causes A to turn high and B to turn low. In this case, the differential output voltage defined as VOD = VA – VB is positive. When D is low, the output states reverse, B turns high, A becomes low, and VOD is negative.

When DE is low, both outputs turn high-impedance. In this condition, the logic state at D is irrelevant.

Table 7-1 Driver Functions
INPUT(1) ENABLE OUTPUTS FUNCTION
D DE A B
H H H L Actively drive bus High
L H L H Actively drive bus Low
X L Z Z Driver disabled
(1) H = high level, L = low level, ? = indeterminate, X = irrelevant, Z = high impedance (off)

When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage defined as VID = VA – VB is positive and higher than the positive input threshold, VIT+, the receiver output (R) turns high. When VID is negative and lower than the negative input threshold, VIT–, the receiver output turns low. If VID is between VIT+ and VIT–, the output is indeterminate.

When RE is logic high, the receiver output is high-impedance and the magnitude and polarity of VID are irrelevant. When the transceiver is disconnected from the bus, the receiver provides a failsafe high output.

Table 7-2 Receiver Functions
DIFFERENTIAL INPUTENABLE(1)OUTPUTFUNCTION
VID = VA – VBRER
VID > VIT+LHReceive valid bus High
VIT– < VID < VIT+L?Indeterminate bus state
VID < VIT–LLReceive valid bus Low
XHZReceiver disabled
OPENLHReceiver failsafe High
(1) H = high level, L = low level, ? = indeterminate, X = irrelevant, Z = high impedance (off)
SN65LBC184 SN75LBC184 Schematic of Inputs and OutputsFigure 7-2 Schematic of Inputs and Outputs