SLLS236J October   1996  – July 2024 SN65LBC184 , SN75LBC184

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: Driver
    6. 5.6  Electrical Characteristics: Receiver
    7. 5.7  Driver Switching Characteristics
    8. 5.8  Receiver Switching Characteristics
    9. 5.9  Dissipation Ratings
    10. 5.10 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Data Rate and Bus Length
        2. 8.2.1.2 Stub Length
        3. 8.2.1.3 Bus Loading
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 SN65LBC184 Test Description
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Driver Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
td(DH)Differential output delay time, low-to-high-level outputRL = 54Ω
CL = 50pF
See Figure 6-41.3μs
td(DL)Differential output delay time, high-to-low-level output1.3μs
tPLHPropagation delay time, low-to-high-level output0.51.3μs
tPHLPropagation delay time, high-to-low-level output0.51.3μs
tsk(p)Pulse skew (| td(DH) – td(DL)|)75150ns
trRise time, single-ended0.251.2μs
tfFall time, single-ended0.251.2μs
tPZHOutput enable time to high levelRL = 110ΩSee Figure 6-13.5μs
tPZLOutput enable time to low levelRL = 110ΩSee Figure 6-23.5μs
tPHZOutput disable time from high levelRL = 110ΩSee Figure 6-12μs
tPLZOutput disable time from low levelRL = 110ΩSee Figure 6-22μs