SLLSEA8A January   2012  – March 2016 SN65LVCP114

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics (VCC 2.5 V ±5%)
    6. 7.6 Electrical Characteristics (VCC 3.3 V ±5%)
    7. 7.7 Electrical Characteristics (VCC 3.3 V ±5%, 2.5 V ±5%)
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Test Circuits
    2. 8.2 Equivalent Input and Output Schematic Diagrams
    3. 8.3 Functional Definitions
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Power Down
      2. 9.3.2  Lane Enable
      3. 9.3.3  Gain and Equalization
      4. 9.3.4  VOD
      5. 9.3.5  AGC
      6. 9.3.6  GPIO or I2C Configuration
      7. 9.3.7  Fast Switching
      8. 9.3.8  Power-Down Input Stages
      9. 9.3.9  Disable Output Lanes
      10. 9.3.10 Polarity Switch
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Mode
      2. 9.4.2 Loopback
      3. 9.4.3 Diagnostic
    5. 9.5 Programming
      1. 9.5.1 Two-Wire Serial Interface and Control Logic
    6. 9.6 Register Maps
      1. 9.6.1 SN65LVCP114 Register Mapping Information
        1. 9.6.1.1  Register 0x00
        2. 9.6.1.2  Register 0x01
        3. 9.6.1.3  Register 0x02
        4. 9.6.1.4  Register 0x03
        5. 9.6.1.5  Register 0x04
        6. 9.6.1.6  Register 0x06
        7. 9.6.1.7  Register 0x07
        8. 9.6.1.8  Register 0x08
        9. 9.6.1.9  Register 0x0A
        10. 9.6.1.10 Register 0x0B
        11. 9.6.1.11 Register 0x0C
        12. 9.6.1.12 Register 0x0D
        13. 9.6.1.13 Register 0x0F
        14. 9.6.1.14 Register 0x10
        15. 9.6.1.15 Register 0x11
        16. 9.6.1.16 Register 0x12
        17. 9.6.1.17 Register Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Transmit-Side Typical Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Receive-Side Typical Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documenation
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Parameter Measurement Information

8.1 Test Circuits

SN65LVCP114 vo_test_cir_llsea8.gif Figure 9. Common-Mode Output-Voltage Test Circuit
SN65LVCP114 Rx_tst_cir_llsea8.gif Figure 10. Receive-Side Performance Test Circuit
SN65LVCP114 Tx_tst_cir_llsea8.gif Figure 11. Transmit-Side Performance Test Circuit

8.2 Equivalent Input and Output Schematic Diagrams

SN65LVCP114 equi_ip_cir_llsea8.gif Figure 12. Equivalent Input Circuit Design
SN65LVCP114 ip_biasing_llsea8.gif Figure 13. 3-Level Input Biasing Network

8.3 Functional Definitions

Table 2. Loopback, Diag, and Sel Controls

LOOP_A LOOP_B LOOP_C DIAG SEL[3:0] OUTPUT PORT A OUTPUT PORT B OUTPUT PORT C
0 0 0 0 0 In_Port_C[3:0] idle In_Port_A[3:0]
0 0 0 0 1 idle In_Port_C[3:0] In_Port_B[3:0]
0 0 0 1 0 In_Port_C[3:0] In_Port_C[3:0] In_Port_A[3:0]
0 0 0 1 1 In_Port_C[3:0] In_Port_C[3:0] In_Port_B[3:0]
0 0 1 0 0 In_Port_C[3:0] Idle In_Port_C[3:0]
0 0 1 0 1 Idle In_Port_C[3:0] In_Port_C[3:0]
0 0 1 1 0 In_Port_C[3:0] In_Port_C[3:0] In_Port_C[3:0]
0 0 1 1 1 In_Port_C[3:0] In_Port_C[3:0] In_Port_C[3:0]
0 1 0 0 0 In_Port_C[3:0] In_Port_B[3:0] In_Port_A[3:0]
0 1 0 0 1 Idle In_Port_B[3:0] In_Port_B[3:0]
0 1 0 1 0 In_Port_C[3:0] In_Port_B[3:0] In_Port_A[3:0]
0 1 0 1 1 In_Port_C[3:0] In_Port_B[3:0] In_Port_B[3:0]
0 1 1 0 0 In_Port_C[3:0] In_Port_B[3:0] In_Port_C[3:0]
0 1 1 0 1 Idle In_Port_B[3:0] In_Port_C[3:0]
0 1 1 1 0 In_Port_C[3:0] In_Port_B[3:0] In_Port_C[3:0]
0 1 1 1 1 In_Port_C[3:0] In_Port_B[3:0] In_Port_C[3:0]
1 0 0 0 0 In_Port_A[3:0] Idle In_Port_A[3:0]
1 0 0 0 1 In_Port_A[3:0] In_Port_C[3:0] In_Port_B[3:0]
1 0 0 1 0 In_Port_A[3:0] In_Port_C[3:0] In_Port_A[3:0]
1 0 0 1 1 In_Port_A[3:0] In_Port_C[3:0] In_Port_B[3:0]
1 0 1 0 0 In_Port_A[3:0] Idle In_Port_C[3:0]
1 0 1 0 1 In_Port_A[3:0] In_Port_C[3:0] In_Port_C[3:0]
1 0 1 1 0 In_Port_A[3:0] In_Port_C[3:0] In_Port_C[3:0]
1 0 1 1 1 In_Port_A[3:0] In_Port_C[3:0] In_Port_C[3:0]
1 1 0 0 0 In_Port_A[3:0] In_Port_B[3:0] In_Port_A[3:0]
1 1 0 0 1 In_Port_A[3:0] In_Port_B[3:0] In_Port_B[3:0]
1 1 0 1 0 In_Port_A[3:0] In_Port_B[3:0] In_Port_A[3:0]
1 1 0 1 1 In_Port_A[3:0] In_Port_B[3:0] In_Port_B[3:0]
1 1 1 0 0 In_Port_A[3:0] In_Port_B[3:0] In_Port_C[3:0]
SN65LVCP114 loopback_mode_llsea8.gif Figure 14. Loopback Mode
SN65LVCP114 diagnostic_mode_llsea8.gif Figure 15. Diagnostic Mode

Table 3. Overall Gain Settings

GAIN_x INPUT GAIN
[dB]		 VOD_x VOD GAIN
[dB]		 EQ[x]0 EQ[x]1 TOTAL DC GAIN
[dB]		 TOTAL EQ GAIN
(7 GHz) [dB]
LOW –6 LOW 1 LOW LOW –5 1.3
LOW –6 LOW 1 LOW HiZ –5 2
LOW –6 LOW 1 LOW HIGH –5 3.6
LOW –6 LOW 1 HiZ LOW –8 5
LOW –6 LOW 1 HiZ HiZ –8 6.5
LOW –6 LOW 1 HiZ HIGH –8 8.3
LOW –6 LOW 1 HIGH LOW –11 10
LOW –6 LOW 1 HIGH HiZ –11 11.9
LOW –6 LOW 1 HIGH HIGH –11 13.9
LOW –6 HIGH 6.8 LOW LOW 0.8 1.3
LOW –6 HIGH 6.8 LOW HiZ 0.8 2
LOW –6 HIGH 6.8 LOW HIGH 0.8 3.6
LOW –6 HIGH 6.8 HiZ LOW –2.2 5
LOW –6 HIGH 6.8 HiZ HiZ –2.2 6.5
LOW –6 HIGH 6.8 HiZ HIGH –2.2 8.3
LOW –6 HIGH 6.8 HIGH LOW –5.2 10
LOW –6 HIGH 6.8 HIGH HiZ –5.2 11.9
LOW –6 HIGH 6.8 HIGH HIGH –5.2 13.9
HIGH 0 LOW 1 LOW LOW 1 1.3
HIGH 0 LOW 1 LOW HiZ 1 2
HIGH 0 LOW 1 LOW HIGH 1 3.6
HIGH 0 LOW 1 HiZ LOW –2 5
HIGH 0 LOW 1 HiZ HiZ –2 6.5
HIGH 0 LOW 1 HiZ HIGH –2 8.3
HIGH 0 LOW 1 HIGH LOW –5 10
HIGH 0 LOW 1 HIGH HiZ –5 11.9
HIGH 0 LOW 1 HIGH HIGH –5 13.9
HIGH 0 HIGH 6.8 LOW LOW 6.8 1.3
HIGH 0 HIGH 6.8 LOW HiZ 6.8 2
HIGH 0 HIGH 6.8 LOW HIGH 6.8 3.6
HIGH 0 HIGH 6.8 HiZ LOW 3.8 5
HIGH 0 HIGH 6.8 HiZ HiZ 3.8 6.5
HIGH 0 HIGH 6.8 HiZ HIGH 3.8 8.3
HIGH 0 HIGH 6.8 HIGH LOW 0.8 10
HIGH 0 HIGH 6.8 HIGH HiZ 0.8 11.9
HIGH 0 HIGH 6.8 HIGH HIGH 0.8 13.9