SLLSEA8A January   2012  – March 2016 SN65LVCP114

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics (VCC 2.5 V ±5%)
    6. 7.6 Electrical Characteristics (VCC 3.3 V ±5%)
    7. 7.7 Electrical Characteristics (VCC 3.3 V ±5%, 2.5 V ±5%)
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Test Circuits
    2. 8.2 Equivalent Input and Output Schematic Diagrams
    3. 8.3 Functional Definitions
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Power Down
      2. 9.3.2  Lane Enable
      3. 9.3.3  Gain and Equalization
      4. 9.3.4  VOD
      5. 9.3.5  AGC
      6. 9.3.6  GPIO or I2C Configuration
      7. 9.3.7  Fast Switching
      8. 9.3.8  Power-Down Input Stages
      9. 9.3.9  Disable Output Lanes
      10. 9.3.10 Polarity Switch
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Mode
      2. 9.4.2 Loopback
      3. 9.4.3 Diagnostic
    5. 9.5 Programming
      1. 9.5.1 Two-Wire Serial Interface and Control Logic
    6. 9.6 Register Maps
      1. 9.6.1 SN65LVCP114 Register Mapping Information
        1. 9.6.1.1  Register 0x00
        2. 9.6.1.2  Register 0x01
        3. 9.6.1.3  Register 0x02
        4. 9.6.1.4  Register 0x03
        5. 9.6.1.5  Register 0x04
        6. 9.6.1.6  Register 0x06
        7. 9.6.1.7  Register 0x07
        8. 9.6.1.8  Register 0x08
        9. 9.6.1.9  Register 0x0A
        10. 9.6.1.10 Register 0x0B
        11. 9.6.1.11 Register 0x0C
        12. 9.6.1.12 Register 0x0D
        13. 9.6.1.13 Register 0x0F
        14. 9.6.1.14 Register 0x10
        15. 9.6.1.15 Register 0x11
        16. 9.6.1.16 Register 0x12
        17. 9.6.1.17 Register Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Transmit-Side Typical Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Receive-Side Typical Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documenation
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

ZJA Package
167-Pin NFBGA
Top View

Pin Functions

PIN DIRECTION TYPE SUPPLY DESCRIPTION
NAME BALLS
LINE-SIDE HIGH-SPEED I/O
CINP0
CINN0		 A12
A13		 Input (with 50-Ω termination to input common mode) Differential input, lane 0 line side.
CINP1
CINN1		 A9
A10		 Input (with 50-Ω termination to input common mode) Differential input, lane 1 line side
CINP2
CINN2		 A6
A7		 Input (with 50-Ω termination to input common mode) Differential input, lane 2 line side
CINP3
CINN3		 A3
A4		 Input (with 50-Ω termination to input common mode) Differential input, lane 3 line side
COUTP0
COUTN0		 C11
C12		 Output Differential output, lane 0 line side
COUTP1
COUTN1		 C8
C9		 Output Differential output, lane 1 line side
COUTP2
COUTN2		 C5
C6		 Output Differential output, lane 2 line side
COUTP3
COUTN3		 C2
C3		 Output Differential output, lane 3 line side
SWITCH-SIDE HIGH-SPEED I/O
AINP0
AINN0		 F14G14 Input (with 50-Ω termination to input common mode) Differential input, lane 0, fabric switch_A_side
AINP1
AINN1		 J14
K14		 Input (with 50-Ω termination to input common mode) Differential input, lane 1, fabric switch_A_side
AINP2
AINN2		 P12
P11		 Input (with 50-Ω termination to input common mode) Differential input, lane 2, fabric switch_A_side
AINP3
AINN3		 P9
P8		 Input (with 50-Ω termination to input common mode) Differential input, lane 3, fabric switch_A_side
BINP0
BINN0		 P6
P5		 Input (with 50-Ω termination to input common mode) Differential input, lane 0, fabric switch_B_side
BINP1
BINN1		 P3
P2		 Input (with 50-Ω termination to input common mode) Differential input, lane 1, fabric switch_B_side
BINP2
BINN2		 J1
H1		 Input (with 50-Ω termination to input common mode) Differential input, lane 2, fabric switch_B_side
BINP3
BINN3		 F1
E1		 Input (with 50-Ω termination to input common mode) Differential input, lane 3, fabric switch_B_side
AOUTP0
AOUTN0		 E12
F12		 Output Differential output, lane 0, fabric switch_A_side
AOUTP1
AOUTN1		 H12
J12		 Output Differential output, lane 1, fabric switch_A_side
AOUTP2
AOUTN2		 M13
M12		 Output Differential output, lane 2, fabric switch_A_side
AOUTP3
AOUTN3		 M10
M9		 Output Differential output, lane 3, fabric switch_A_side
BOUTP0
BOUTN0		 M7
M6		 Output Differential output, lane 0, fabric switch_B_side
BOUTP1
BOUTN1		 M4
M3		 Output Differential output, lane 1, fabric switch_B_side
BOUTP2
BOUTN2		 K3
J3		 Output Differential output, lane 2, fabric switch_B_side
BOUTP3
BOUTN3		 G3
F3		 Output Differential output, lane 3, fabric switch_B_side
CONTROL SIGNALS
ADD0/EQA1
ADD1/EQB1
ADD2/EQC1		 A14
B14
A1		 Input, 2.5-V or 3.3-V CMOS - 3-state GPIO mode
EQ control pins. EQA1 and EQA0 pins are 3-state and control the EQ gain of port A.
EQ control pins. EQB1 and EQB0 pins are 3-state and control the EQ gain of port B.
EQ control pins. EQC1 and EQC0 pins are 3-state and control the EQ gain of port C.
Refer to Table 5 for detailed information about equalization.		 I2C mode
ADD0 along with pins ADD1 and ADD2 comprise the three bits of the I2C slave address.
EQA0
EQB0
EQC0		 D3
K1
C14		 Input, 2.5-V or 3.3-V CMOS - 3-state GPIO mode
EQ control pins. EQA1 and EQA0 pins are 3-state and control theEQ gain of port A.
EQ control pins. EQB1 and EQB0 pins are 3-state and control theEQ gain of port B.
EQ control pins. EQC1 and EQC0 pins are 3-state and control theEQ gain of port C.
Refer to Table 5 for detailed information about equalization.		 I2C mode
No action needed
LPA
LPB
LPC		 P14
N14
M14		 Input (with 48-kΩ pulldown)
2.5-V or 3.3-V CMOS		 GPIO mode
LPx enables loopback for port x
HIGH: Loopback enabled
LOW: Loopback disabled
See Table 2 and Figure 14		 I2C mode
No action needed
SEL0
SEL1
SEL2
SEL3		 P1
N1
M1
L1		 Input (with 48-kΩ pulldown)
2.5-V or 3.3-V CMOS		 GPIO mode
SELx, A or B switch control for lane x
HIGH: port B is selected
LOW: port A is selected
See Table 2		 I2C mode
No action needed
REXT P13 Input, analog External bias resistor, 1,200 Ω to ground
CS C13 Input (with 48-kΩ pulldown)
2.5-V or 3.3-V CMOS		 GPIO mode
No action needed		 I2C mode
HIGH: acts as chip select
LOW: disables I2C interface
PWDn E14 Input (with 48-kΩ pullup)
2.5-V or 3.3-V CMOS		 LOW: Powers down the device, inputs off and outputs disabled, resets I2C
HIGH: Normal operation
DIAG L12 Input (with 48-kΩ pulldown)
2.5-V or 3.3-V CMOS		 GPIO mode
HIGH: Enables the same data on the line side (Port C) to be output on both fabric side ports (Port A and Port B).
LOW: Normal operation
See Table 2 and Figure 15		 I2C mode
No action needed
LN_0_EN
LN_1_EN
LN_2_EN
LN_3_EN		 K12
K13
L14
L13		 Input (with 48-kΩ pullup)
2.5-V or 3.3-V CMOS		 GPIO mode
LN_x_EN = High, enables lane x of ports A, B, and C
LN_x_EN = Low, disables lane x of ports A, B, and C		 I2C mode
No action needed
DIS_AGC_A
DIS_AGC_B
DIS_AGC_C		 B1
C1
D1		 Input (with 48-kΩ pulldown)
2.5-V or 3.3-V CMOS		 GPIO mode
Disables the AGC loop internal to the SN65LVCP114
DIS_AGC = High, disables the AGC loop
DIS_AGC = Low, enables the AGC loop		 I2C mode
No action needed
VOD_A
VOD_B
VOD_C		 N2
M2
L2		 Input, 2.5-V or 3.3-V CMOS - 3-state GPIO mode
HIGH: selects VOD output range: 1.2 V maximum and a gain of 2.2
LOW: selects VOD output range: 600 mV maximum and a gain of 1.1
If the VOD_x signal is left floating, the signal defaults to 1.2 V maximum and a gain of 2.2		 I2C mode
No action needed
Gain_A
Gain_B
Gain_C		 E2
D2
E3		 Input, 2.5-V or 3.3-V CMOS - 3-state GPIO mode
HIGH: Receiver gain = 1
LOW: Receiver gain = 0.5
If the Gain_x signal is left floating, the signal defaults to 0.5		 I2C mode
No action needed
SDA A2 Input / output, open-drain output GPIO mode
No action needed		 I2C mode
I2C data. Connect a 10-kΩ pullup resistor externally
SCL B2 Input, open-drain input GPIO mode
No action needed		 I2C mode
I2C clock. Connect a 10-kΩ pullup resistor externally
FST_SW D13 Input (with 48-kΩ pullup)
2.5-V or 3.3-V CMOS input		 GPIO mode
HIGH: Fast switching; the idle outputs are squelched (see tSM specification).
LOW: Slow switching; the idle outputs are powered off (see tSM1 specification).		 I2C mode
No action needed
I2C_SEL D14 Input (with 48-kΩ pulldown)
2.5-V or 3.3-V CMOS input		 Configures the device in I2C or GPIO mode of operation
HIGH: Enables I2C mode
LOW: Enables GPIO mode
POWER SUPPLY
VCC B4, B5, B7, B8, B10, B11, B13, E13, G2, G13, H2, H13, K2,N4, N5, N7, N10, N11, N13 Power, 2.5 V ±5% or 3.3 V ±5% Power supply pins
GROUND
GND A5, A8, A11, B3, B6, B9, B12, C4, C7, C10,D12, F2, F13,G1, G12, G1, G12, H3, H14,J2, J13, L3, M5,M8, M11, N3, N6, N8, N9, N12, P4, P7, P10 Ground Ground pins
GND_CenterPad E6, E7 , E8, E9, E10, F5, F6, F7, F8, F9, F10, G5, G6, G7,G8, G9, G10, H5, H6, H7, H8, H9, H10, J5, J6, J7, J8, J9, J10, K5, K6, K7,K8, K9, K10 Ground These pins must be connected to the GND plane.