SLLS373M July   1999  – March 2024 SN65LVDS1 , SN65LVDS2 , SN65LVDT2

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Driver Electrical Characteristics
    6. 6.6 Receiver Electrical Characteristics
    7. 6.7 Driver Switching Characteristics
    8. 6.8 Receiver Switching Characteristics
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 SN65LVDS1 Features
        1. 8.3.1.1 Driver Output Voltage and Power-On Reset
        2. 8.3.1.2 Driver Offset
        3. 8.3.1.3 5-V Input Tolerance
        4. 8.3.1.4 NC Pins
        5. 8.3.1.5 Driver Equivalent Schematics
      2. 8.3.2 SN65LVDS2 and SN65LVDT2 Features
        1. 8.3.2.1 Receiver Open Circuit Fail-Safe
        2. 8.3.2.2 Receiver Output Voltage and Power-On Reset
        3. 8.3.2.3 Common-Mode Range vs Supply Voltage
        4. 8.3.2.4 General Purpose Comparator
        5. 8.3.2.5 Receiver Equivalent Schematics
        6. 8.3.2.6 NC Pins
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation With VCC < 1.5 V
      2. 8.4.2 Operation With 1.5 V ≤ VCC < 2.4 V
      3. 8.4.3 Operation With 2.4 V ≤ VCC < 3.6 V
      4. 8.4.4 SN65LVDS1 Truth Table
      5. 8.4.5 SN65LVDS2 and SN65LVDT2 Truth Table
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Point-to-Point Communications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Driver Supply Voltage
          2. 9.2.1.2.2  Driver Bypass Capacitance
          3. 9.2.1.2.3  Driver Input Voltage
          4. 9.2.1.2.4  Driver Output Voltage
          5. 9.2.1.2.5  Interconnecting Media
          6. 9.2.1.2.6  PCB Transmission Lines
          7. 9.2.1.2.7  Termination Resistor
          8. 9.2.1.2.8  Driver NC Pins
          9. 9.2.1.2.9  Receiver Supply Voltage
          10. 9.2.1.2.10 Receiver Bypass Capacitance
          11. 9.2.1.2.11 Receiver Input Common-Mode Range
          12. 9.2.1.2.12 Receiver Input Signal
          13. 9.2.1.2.13 Receiver Output Signal
          14. 9.2.1.2.14 Receiver NC Pins
      2. 9.2.2 Application Curve
      3. 9.2.3 Multidrop Communications
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1 Interconnecting Media
        3. 9.2.3.3 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Microstrip vs. Stripline Topologies
      2. 11.1.2 Dielectric Type and Board Construction
      3. 11.1.3 Recommended Stack Layout
      4. 11.1.4 Separation Between Traces
      5. 11.1.5 Crosstalk and Ground Bounce Minimization
      6. 11.1.6 Decoupling
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Other LVDS Products
    2. 12.2 Third-Party Products Disclaimer
    3. 12.3 Documentation Support
      1. 12.3.1 Related Information
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Support Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DBV|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information
9.2.1.2.2 Driver Bypass Capacitance

Bypass capacitors play a key role in power distribution circuitry. Specifically, they create low-impedance paths between power and ground. At low frequencies, a good digital power supply offers very low-impedance paths between its terminals. However, as higher frequency currents propagate through power traces, the source is quite often incapable of maintaining a low-impedance path to ground. Bypass capacitors are used to address this shortcoming. Usually, large bypass capacitors (10 μF to 1000 μF) at the board-level do a good job up into the kHz range. Due to their size and length of their leads, they tend to have large inductance values at the switching frequencies of modern digital circuitry. To solve this problem, one must resort to the use of smaller capacitors (nF to μF range) installed locally next to the integrated circuit.

Multilayer ceramic chip or surface-mount capacitors (size 0603 or 0805) minimize lead inductances of bypass capacitors in high-speed environments, because their lead inductance is about 1 nH. For comparison purposes, a typical capacitor with leads has a lead inductance around 5 nH.

The value of the bypass capacitors used locally with LVDS chips can be determined by the following formula according to Johnson1, equations 8.18 to 8.21. A conservative rise time of 200 ps and a worst-case change in supply current of 1 A covers the whole range of LVDS devices offered by Texas Instruments. In this example, the maximum power supply noise tolerated is 200 mV; however, this figure varies depending on the noise budget available in your design.

Equation 1. SN65LVDS1 SN65LVDS2 SN65LVDT2
Equation 2. SN65LVDS1 SN65LVDS2 SN65LVDT2

The following example lowers lead inductance and covers intermediate frequencies between the board-level capacitor (>10 µF) and the value of capacitance found above (0.001 µF). You should place the smallest value of capacitance as close as possible to the chip.

SN65LVDS1 SN65LVDS2 SN65LVDT2 Recommended LVDS Bypass Capacitor Layout Figure 9-2 Recommended LVDS Bypass Capacitor Layout
  1. Howard Johnson & Martin Graham.1993. High Speed Digital Design – A Handbook of Black Magic. Prentice Hall PRT. ISBN number 013395724.