SLLS516E August   2002  – July 2015 SN65LVDS100 , SN65LVDS101 , SN65LVDT100 , SN65LVDT101

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Device Options
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Switching Characteristics
    7. 8.7 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Receiver Features
        1. 10.3.1.1 Voltage Range and Common-Mode Range
        2. 10.3.1.2 Sensitivity
        3. 10.3.1.3 Failsafe Considerations
        4. 10.3.1.4 VBB Voltage Reference
        5. 10.3.1.5 Integrated Termination
        6. 10.3.1.6 Receiver Equivalent Schematic
      2. 10.3.2 Driver Features
        1. 10.3.2.1 Signaling Rate, Edge Rate, and Added Jitter
        2. 10.3.2.2 SN65LVDx100 LVDS Output
          1. 10.3.2.2.1 Driver Output Voltage
          2. 10.3.2.2.2 Driver Offset
        3. 10.3.2.3 SN65LVDx101 LVPECL Output
          1. 10.3.2.3.1 Driver Voltage
        4. 10.3.2.4 Driver Equivalent Schematics
    4. 10.4 Device Functional Modes
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 PECL to LVDS Translation
        1. 11.2.1.1 Design Requirements
        2. 11.2.1.2 Detailed Design Requirements
        3. 11.2.1.3 Application Curve
      2. 11.2.2 LVDS to 3.3-V PECL Translation
        1. 11.2.2.1 Design Requirements
        2. 11.2.2.2 Detailed Design Requirements
        3. 11.2.2.3 Application Curve
      3. 11.2.3 5-V PECL to 3.3-V PECL Translation
        1. 11.2.3.1 Design Requirements
        2. 11.2.3.2 Detailed Design Requirements
        3. 11.2.3.3 Application Curve
      4. 11.2.4 CML to LVDS or 3.3-V PECL Translation
        1. 11.2.4.1 Design Requirements
        2. 11.2.4.2 Detailed Design Requirements
        3. 11.2.4.3 Application Curve
      5. 11.2.5 Single-Ended 3.3-V PECL to LVDS Translation
        1. 11.2.5.1 Design Requirements
        2. 11.2.5.2 Detailed Design Requirements
        3. 11.2.5.3 Application Curve
      6. 11.2.6 Single-Ended CMOS to LVDS Translation
        1. 11.2.6.1 Design Requirements
        2. 11.2.6.2 Detailed Design Requirements
        3. 11.2.6.3 Application Curve
      7. 11.2.7 Single-Ended CMOS to 3.3-V PECL Translation
        1. 11.2.7.1 Design Requirements
        2. 11.2.7.2 Detailed Design Requirements
        3. 11.2.7.3 Application Curve
      8. 11.2.8 Receipt of AC-Coupled Signals
        1. 11.2.8.1 Design Requirements
        2. 11.2.8.2 Detailed Design Requirements
        3. 11.2.8.3 Application Curve
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 Microstrip vs. Stripline Topologies
      2. 13.1.2 Dielectric Type and Board Construction
      3. 13.1.3 Recommended Stack Layout
      4. 13.1.4 Separation Between Traces
      5. 13.1.5 Crosstalk and Ground Bounce Minimization
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Related Links
    2. 14.2 Community Resources
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DGK|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

13 Layout

13.1 Layout Guidelines

13.1.1 Microstrip vs. Stripline Topologies

As per SLLD009, modern printed-circuit boards usually offer designers two transmission line options: Microstrip and stripline. Microstrips are traces on the outer layer of a PCB, as shown in Figure 51.

SN65LVDS100 SN65LVDT100 SN65LVDS101 SN65LVDT101 lo_mt_slls373.pngFigure 51. Microstrip Topology

On the other hand, striplines are traces between two ground planes. Striplines are less prone to emissions and susceptibility problems since the reference planes effectively shield the embedded traces. However, from the standpoint of high-speed transmission, juxtaposing two planes creates additional capacitance. TI recommends routing LVDS signals on microstrip transmission lines, if possible. The PCB traces allow designers to specify the necessary tolerances for ZO based on the overall noise budget and reflection allowances. Footnotes 1(1), 2(2), and 3(3) provide formulas for ZO and tPD for differential and single-ended traces.

(1) Howard Johnson & Martin Graham.1993. High Speed Digital Design – A Handbook of Black Magic. Prentice Hall PRT. ISBN number 013395724.
(2) Mark I. Montrose. 1996. Printed Circuit Board Design Techniques for EMC Compliance. IEEE Press. ISBN number 0780311310.
(3) Clyde F. Coombs, Jr. Ed, Printed Circuits Handbook, McGraw Hill, ISBN number 0070127549.

SN65LVDS100 SN65LVDT100 SN65LVDS101 SN65LVDT101 lo_st_slls373.pngFigure 52. Stripline Topology

13.1.2 Dielectric Type and Board Construction

The speeds at which signals travel across the board dictates the choice of dielectric. FR-4, or equivalent, usually provides adequate performance for use with LVDS signals. If rise or fall times of TTL/CMOS signals are less than 500 ps, empirical results indicate that a material with a dielectric constant near 3.4, such as Rogers™ 4350 or Nelco N4000-13 is better suited. Once the designer chooses the dielectric, there are several parameters pertaining to the board construction that can affect performance. The following set of guidelines were developed experimentally through several designs involving LVDS devices:

  • Copper weight: 15 g or 1/2 oz start, plated to 30 g or 1 oz
  • All exposed circuitry should be solder-plated (60/40) to 7.62 μm or 0.0003 in (minimum).
  • Copper plating should be 25.4 μm or 0.001 in (minimum) in plated-through-holes.
  • Solder mask over bare copper with solder hot-air leveling

13.1.3 Recommended Stack Layout

Following the choice of dielectrics and design specifications, you must decide how many levels to use in the stack. To reduce the TTL/CMOS-to-LVDS crosstalk, it is a good practice to have at least two separate signal planes as shown in Figure 53.

SN65LVDS100 SN65LVDT100 SN65LVDS101 SN65LVDT101 lo_4lpcbb_slls373.gifFigure 53. Four-Layer PCB Board

NOTE

The separation between layers 2 and 3 should be 127 μm (0.005 in). By keeping the power and ground planes tightly coupled, the increased capacitance acts as a bypass for transients.

One of the most common stack configurations is the six-layer board, as shown in Figure 54.

SN65LVDS100 SN65LVDT100 SN65LVDS101 SN65LVDT101 lo_6lpcbb_slls373.gifFigure 54. Six-Layer PCB Board

In this particular configuration, it is possible to isolate each signal layer from the power plane by at least one ground plane. The result is improved signal integrity; however, fabrication is more expensive. Using the 6-layer board is preferable, since it offers the layout designer more flexibility in varying the distance between signal layers and referenced planes, in addition to ensuring reference to a ground plane for signal layers 1 and 6.

13.1.4 Separation Between Traces

The separation between traces depends on several factors; however, the amount of coupling that can be tolerated usually dictates the actual separation. Low-noise coupling requires close coupling between the differential pair of an LVDS link to benefit from the electromagnetic field cancellation. The traces should be 100-Ω differential and thus coupled in the manner that best fits this requirement. In addition, differential pairs should have the same electrical length to ensure that they are balanced, thus minimizing problems with skew and signal reflection.

In the case of two adjacent single-ended traces, one should use the 3-W rule, which stipulates that the distance between two traces must be greater than two times the width of a single trace, or three times its width measured from trace center to trace center. This increased separation effectively reduces the potential for crosstalk. The same rule should be applied to the separation between adjacent LVDS differential pairs, whether the traces are edge-coupled or broadside-coupled.

SN65LVDS100 SN65LVDT100 SN65LVDS101 SN65LVDT101 lo_3wrsedt_slls373.gifFigure 55. 3-W Rule for Single-Ended and Differential Traces (Top View)

You should exercise caution when using autorouters, because they do not always account for all factors affecting crosstalk and signal reflection. For instance, it is best to avoid sharp 90° turns to prevent discontinuities in the signal path. Using successive 45° turns tends to minimize reflections.

13.1.5 Crosstalk and Ground Bounce Minimization

To reduce crosstalk, it is important to provide a return path for high-frequency currents that is as close as possible to its originating trace. A ground plane usually achieves this. Because the returning currents always choose the path of lowest inductance, they are most likely to return directly under the original trace, thus minimizing crosstalk. Lowering the area of the current loop lowers the potential for crosstalk. Traces kept as short as possible with an uninterrupted ground plane running beneath them emit the minimum amount of electromagnetic field strength. Discontinuities in the ground plane increase the return path inductance and should be avoided.

13.2 Layout Example

See Layout Guidelines examples.

At least two or three times the width of an individual trace should separate single-ended traces and differential pairs to minimize the potential for crosstalk. Single-ended traces that run in parallel for less than the wavelength of the rise or fall times usually have negligible crosstalk. Increase the spacing between signal paths for long parallel runs to reduce crosstalk. Boards with limited real estate can benefit from the staggered trace layout, as shown in Figure 56.

SN65LVDS100 SN65LVDT100 SN65LVDS101 SN65LVDT101 lo_stl_slls373.gifFigure 56. Staggered Trace Layout

This configuration lays out alternating signal traces on different layers; thus, the horizontal separation between traces can be less than 2 or 3 times the width of individual traces. To ensure continuity in the ground signal path, TI recommends having an adjacent ground via for every signal via, as shown in Figure 57. Note that vias create additional capacitance. For example, a typical via has a lumped capacitance effect of 1/2 pF to 1 pF in FR4.

SN65LVDS100 SN65LVDT100 SN65LVDS101 SN65LVDT101 lo_gvasv_slls373.gifFigure 57. Ground Via Location (Side View)

Short and low-impedance connection of the device's ground pins to the PCB ground plane reduces ground bounce. Holes and cutouts in the ground planes can adversely affect current return paths if they create discontinuities that increase returning current loop areas.

To minimize EMI problems, TI recommends avoiding discontinuities below a trace (for example, holes, slits, and so on) and keeping traces as short as possible. Zoning the board wisely by placing all similar functions in the same area, as opposed to mixing them together, helps reduce susceptibility issues.