SLLS516E August   2002  – July 2015 SN65LVDS100 , SN65LVDS101 , SN65LVDT100 , SN65LVDT101

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Device Options
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Switching Characteristics
    7. 8.7 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Receiver Features
        1. 10.3.1.1 Voltage Range and Common-Mode Range
        2. 10.3.1.2 Sensitivity
        3. 10.3.1.3 Failsafe Considerations
        4. 10.3.1.4 VBB Voltage Reference
        5. 10.3.1.5 Integrated Termination
        6. 10.3.1.6 Receiver Equivalent Schematic
      2. 10.3.2 Driver Features
        1. 10.3.2.1 Signaling Rate, Edge Rate, and Added Jitter
        2. 10.3.2.2 SN65LVDx100 LVDS Output
          1. 10.3.2.2.1 Driver Output Voltage
          2. 10.3.2.2.2 Driver Offset
        3. 10.3.2.3 SN65LVDx101 LVPECL Output
          1. 10.3.2.3.1 Driver Voltage
        4. 10.3.2.4 Driver Equivalent Schematics
    4. 10.4 Device Functional Modes
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 PECL to LVDS Translation
        1. 11.2.1.1 Design Requirements
        2. 11.2.1.2 Detailed Design Requirements
        3. 11.2.1.3 Application Curve
      2. 11.2.2 LVDS to 3.3-V PECL Translation
        1. 11.2.2.1 Design Requirements
        2. 11.2.2.2 Detailed Design Requirements
        3. 11.2.2.3 Application Curve
      3. 11.2.3 5-V PECL to 3.3-V PECL Translation
        1. 11.2.3.1 Design Requirements
        2. 11.2.3.2 Detailed Design Requirements
        3. 11.2.3.3 Application Curve
      4. 11.2.4 CML to LVDS or 3.3-V PECL Translation
        1. 11.2.4.1 Design Requirements
        2. 11.2.4.2 Detailed Design Requirements
        3. 11.2.4.3 Application Curve
      5. 11.2.5 Single-Ended 3.3-V PECL to LVDS Translation
        1. 11.2.5.1 Design Requirements
        2. 11.2.5.2 Detailed Design Requirements
        3. 11.2.5.3 Application Curve
      6. 11.2.6 Single-Ended CMOS to LVDS Translation
        1. 11.2.6.1 Design Requirements
        2. 11.2.6.2 Detailed Design Requirements
        3. 11.2.6.3 Application Curve
      7. 11.2.7 Single-Ended CMOS to 3.3-V PECL Translation
        1. 11.2.7.1 Design Requirements
        2. 11.2.7.2 Detailed Design Requirements
        3. 11.2.7.3 Application Curve
      8. 11.2.8 Receipt of AC-Coupled Signals
        1. 11.2.8.1 Design Requirements
        2. 11.2.8.2 Detailed Design Requirements
        3. 11.2.8.3 Application Curve
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 Microstrip vs. Stripline Topologies
      2. 13.1.2 Dielectric Type and Board Construction
      3. 13.1.3 Recommended Stack Layout
      4. 13.1.4 Separation Between Traces
      5. 13.1.5 Crosstalk and Ground Bounce Minimization
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Related Links
    2. 14.2 Community Resources
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DGK|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Power Supply Recommendations

The LVDS drivers in this data sheet are designed to operate from a single power supply, with supply voltages in the range of 3.0 V to 3.6 V. In a typical application, a driver and a receiver may be on separate boards, or even separate equipment. In these cases, separate supplies would be used at each location. The expected ground potential difference between the driver power supply and the receiver power supply would be less than |±1 V|. Board level and local device level bypass capacitance should be used and have been covered.