SLLS396G SEPTEMBER   1999  – December 2015 SN65LVDS104 , SN65LVDS105

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Selection Guide to LVDS Repeaters
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings—JEDEC
    3. 7.3  ESD Ratings—MIL-STD
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  SN65LVDS104 Electrical Characteristics
    7. 7.7  SN65LVDS105 Electrical Characteristics
    8. 7.8  SN65LVDS104 Switching Characteristics
    9. 7.9  SN65LVDS105 Switching Characteristics
    10. 7.10 Dissipation Ratings
    11. 7.11 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fail Safe
    4. 9.4 Device Functional Modes
      1. 9.4.1 Input Level Translation
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Point-to-Point Communications
      2. 10.2.2 Design Requirements
      3. 10.2.3 Detailed Design Procedure
        1. 10.2.3.1  Bypass Capacitance
        2. 10.2.3.2  Driver Supply Voltage
        3. 10.2.3.3  Driver Input Voltage
        4. 10.2.3.4  Driver Output Voltage
        5. 10.2.3.5  Interconnecting Media
        6. 10.2.3.6  PCB Transmission Lines
        7. 10.2.3.7  Termination Resistor
        8. 10.2.3.8  Receiver Supply Voltage
        9. 10.2.3.9  Receiver Input Common-Mode Range
        10. 10.2.3.10 Receiver Input Signal
        11. 10.2.3.11 Receiver Output Signal
      4. 10.2.4 Application Curve
    3. 10.3 Multidrop Communications
      1. 10.3.1 Design Requirements
      2. 10.3.2 Detailed Design Procedure
        1. 10.3.2.1 Interconnecting Media
  11. 11Power Supply Recommendations
    1. 11.1 Coupling Capacitor Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Microstrip vs. Stripline Topologies
      2. 12.1.2 Dielectric Type and Board Construction
      3. 12.1.3 Recommended Stack Layout
      4. 12.1.4 Separation Between Traces
      5. 12.1.5 Crosstalk and Ground Bounce Minimization
      6. 12.1.6 Decoupling
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|16
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Power Supply Recommendations

11.1 Coupling Capacitor Recommendations

To minimize the power supply noise floor, provide good decoupling near the SN65LVDS10x power pins. It is recommended to place one 0.01-μF ceramic capacitor at each power pin, and two 0.1-μF ceramic capacitors on each power node. The distance between the device and capacitors must be minimized to reduce loop inductance and provide optimal noise filtering. Placing the capacitor underneath the device on the bottom of the PCB is often a good choice. A 100-pF ceramic capacitor can be put at each power pin to optimize the EMI performance.