SLLS301R APRIL   1998  – January 2016 SN65LVDS050 , SN65LVDS051 , SN65LVDS179 , SN65LVDS180

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Device Options
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Device Electrical Characteristics
    6. 8.6  Driver Electrical Characteristics
    7. 8.7  Receiver Electrical Characteristics
    8. 8.8  Driver Switching Characteristics
    9. 8.9  Receiver Switching Characteristics
    10. 8.10 Typical Characteristics
  9. 9 Parameter Measurement Information
    1. 9.1 Driver
    2. 9.2 Receiver
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Driver Offset
      2. 10.3.2 5-V Input Tolerance
      3. 10.3.3 NC Pins
      4. 10.3.4 Driver Equivalent Schematics
      5. 10.3.5 Receiver Features
        1. 10.3.5.1 Receiver Output States
        2. 10.3.5.2 Receiver Open-Circuit Fail-Safe
        3. 10.3.5.3 Receiver Power-On Reset
        4. 10.3.5.4 Common-Mode Range vs Supply Voltage
        5. 10.3.5.5 General Purpose Comparator
        6. 10.3.5.6 Receiver Equivalent Schematics
    4. 10.4 Device Functional Modes
      1. 10.4.1 Function Tables
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Equipment
        2. 11.2.2.2 Driver Supply Voltage
        3. 11.2.2.3 Driver Bypass Capacitance
        4. 11.2.2.4 Driver Output Voltage
        5. 11.2.2.5 Interconnecting Media
        6. 11.2.2.6 PCB Transmission Lines
        7. 11.2.2.7 Termination Resistor
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 Microstrip vs. Stripline Topologies
      2. 13.1.2 Dielectric Type and Board Construction
      3. 13.1.3 Recommended Stack Layout
      4. 13.1.4 Separation Between Traces
      5. 13.1.5 Crosstalk and Ground Bounce Minimization
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Device Support
      1. 14.1.1 Third-Party Products Disclaimer
      2. 14.1.2 Other LVDS Products
    2. 14.2 Documentation Support
      1. 14.2.1 Related Information
    3. 14.3 Related Links
    4. 14.4 Trademarks
    5. 14.5 Electrostatic Discharge Caution
    6. 14.6 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • PW|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Parameter Measurement Information

9.1 Driver

SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051 dvacd_slls301.gif Figure 10. Driver Voltage and Current Definitions
SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051 difsig_lls301.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0.06 mm of the device under test.
Figure 11. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051 drivolt_lls301.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0.06 mm of the device under test. The measurement of VOC(PP) is made on test equipment with a –3-dB bandwidth of at least 300 MHz.
Figure 12. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051 circdef_lls301.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0.06 mm of the device under test.
Figure 13. Enable or Disable Time Circuit and Definitions

9.2 Receiver

SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051 voltdef_lls301.gif Figure 14. Receiver Voltage Definitions

Table 2. Receiver Minimum And Maximum Input Threshold Test Voltages

APPLIED VOLTAGES RESULTING DIFFERENTIAL
INPUT VOLTAGE 		RESULTING COMMON-MODE
INPUT VOLTAGE
VIA (V) VIB (V) VID (mV) VIC (V)
1.25 1.15 100 1.2
1.15 1.25 –100 1.2
2.4 2.3 100 2.35
2.3 2.4 –100 2.35
0.1 0 100 0.05
0 0.1 –100 0.05
1.5 0.9 600 1.2
0.9 1.5 –600 1.2
2.4 1.8 600 2.1
1.8 2.4 –600 2.1
0.6 0 600 0.3
0 0.6 –600 0.3
SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051 ttcaw_slls301.gif
SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051 circwav2_lls301.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0.06 m of the device under test.
Figure 15. Timing Test Circuit and Waveforms
SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051 circwav3_lls301.gif
SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051 circwav4_lls301.gif
SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051 circwav5_lls301.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0.06 m of the device under test.
Figure 16. Enable or Disable Time Test Circuit and Waveforms