SLLS362G SEPTEMBER 1999 – January 2016 SN65LVDS387 , SN65LVDS389 , SN65LVDS391 , SN75LVDS387 , SN75LVDS389 , SN75LVDS391
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
This family of 4, 8, and 16 differential line drivers implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the 16 current-mode drivers will deliver a minimum differential output voltage magnitude of 247 mV into a 100-Ω load when enabled.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
SN65LVDS387 | TSSOP (64) | 17.00 mm × 6.10 mm |
SN75LVDS387 | TSSOP (38) | 9.70 mm × 4.40 mm |
SN65LVDS389 | SOIC (16) | 9.90 mm × 3.91 mm |
TSSOP (16) | 5.00 mm × 4.40 mm | |
SN75LVDS389 | TSSOP (64) | 17.00 mm × 6.10 mm |
SN65LVDS391 | TSSOP (38) | 9.70 mm × 4.40 mm |
SN75LVDS391 | SOIC (16) | 9.90 mm × 3.91 mm |
TSSOP (16) | 5.00 mm × 4.40 mm |
Changes from F Revision (December 2014) to G Revision
Changes from E Revision (November 2004) to F Revision
When disabled, the driver outputs are high-impedance. Each driver input (A) and enable (EN) have an internal pulldown that will drive the input to a low level when open-circuited.
The SN65LVDS387, SN65LVDS389, and SN65LVDS391 devices are characterized for operation from –40°C to 85°C. The SN75LVDS387, SN75LVDS389, and SN75LVDS391 devices are characterized for operation from 0°C to 70°C.
PART NUMBER(1) | TEMPERATURE RANGE | NUMBER OF DRIVERS | BUS-PIN ESD |
---|---|---|---|
SN65LVDS387DGG | –40°C to 85°C | 16 | 15 kV |
SN75LVDS387DGG | 0°C to 70°C | 16 | 4 kV |
SN65LVDS389DBT | –40°C to 85°C | 8 | 15 kV |
SN75LVDS389DBT | 0°C to 70°C | 8 | 4 kV |
SN65LVDS391D | –40°C to 85°C | 4 | 15 kV |
SN75LVDS391D | 0°C to 70°C | 4 | 4 kV |
SN65LVDS391PW | –40°C to 85°C | 4 | 15 kV |
SN75LVDS391PW | 0°C to 70°C | 4 | 4 kV |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NUMBER | ||
VCC | 4 | – | Supply voltage |
GND | 5 | – | Ground |
1A | 2 | I | LVTTL input signal |
1Y | 16 | O | Differential (LVDS) non-inverting output |
1Z | 15 | O | Differential (LVDS) inverting output |
2A | 3 | I | LVTTL input signal |
2Y | 14 | O | Differential (LVDS) non-inverting output |
2Z | 13 | O | Differential (LVDS) inverting output |
3A | 6 | I | LVTTL input signal |
3Y | 12 | O | Differential (LVDS) non-inverting output |
3Z | 11 | O | Differential (LVDS) inverting output |
4A | 7 | I | LVTTL input signal |
4Y | 10 | O | Differential (LVDS) non-inverting output |
4Z | 9 | O | Differential (LVDS) inverting output |
EN1,2 | 1 | I | Enable for channels 1 and 2 |
EN3,4 | 8 | I | Enable for channels 3 and 4 |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NUMBER | ||
VCC | 2, 10, 18 | – | Supply voltage |
GND | 1, 3, 9, 11, 17, 19 | – | Ground |
A1A | 5 | I | LVTTL input signal |
A1Y | 38 | O | Differential (LVDS) non-inverting output |
A1Z | 37 | O | Differential (LVDS) inverting output |
A2A | 6 | I | LVTTL input signal |
A2Y | 36 | O | Differential (LVDS) non-inverting output |
A2Z | 35 | O | Differential (LVDS) inverting output |
A3A | 7 | I | LVTTL input signal |
A3Y | 34 | O | Differential (LVDS) non-inverting output |
A3Z | 33 | O | Differential (LVDS) inverting output |
A4A | 8 | I | LVTTL input signal |
A4Y | 32 | O | Differential (LVDS) non-inverting output |
A4Z | 31 | O | Differential (LVDS) inverting output |
B1A | 12 | I | LVTTL input signal |
B1Y | 27 | O | Differential (LVDS) non-inverting output |
B1Z | 26 | O | Differential (LVDS) inverting output |
B2A | 13 | I | LVTTL input signal |
B2Y | 25 | O | Differential (LVDS) non-inverting output |
B2Z | 24 | O | Differential (LVDS) inverting output |
B3A | 14 | I | LVTTL input signal |
B3Y | 23 | O | Differential (LVDS) non-inverting output |
B3Z | 22 | O | Differential (LVDS) inverting output |
B4A | 15 | I | LVTTL input signal |
B4Y | 21 | O | Differential (LVDS) non-inverting output |
B4B | 20 | O | Differential (LVDS) inverting output |
ENA | 4 | I | Enable for channel A |
ENB | 16 | I | Enable for channel B |
NC | 28, 29, 30 | – | No connection |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage range, VCC(2) | –0.5 | 4 | V | |
Input voltage range | Inputs | –0.5 | 6 | V |
Y or Z | –0.5 | 4 | V | |
Continuous power dissipation | See Thermal Information | |||
Lead temperature 1.6 mm (1/16 in) from case for 10 seconds | 260 | °C | ||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | SN65' (Y, Z, and GND) | Class 3, A | ±15000 | V |
Class 3, B | ±400 | V | |||
SN75' (Y, Z, and GND) | Class 3, A | ±4000 | V | ||
Class 3, B | ±400 | V | |||
Lead temperature 1.6 mm (1/16 in) from case for 10 seconds | 260 | °C |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VCC | Supply voltage | 3 | 3.3 | 3.6 | V | |
VIH | High-level input voltage | 2 | V | |||
VIL | Low-level input voltage | 0.8 | V | |||
TA | Operating free-air temperature | SN75' | 0 | 70 | °C | |
SN65' | –40 | 85 | °C |
THERMAL METRIC(1) | SN65LVDS387 SN75LVDS389 | SN75LVDS387 SN65LVDS391 | SN65LVDS389 SN75LVDS391 | UNIT | ||
---|---|---|---|---|---|---|
DGG | DBT | D | PW | |||
64 PINS | 38 PINS | 16 PINS | 16 PINS | |||
Derating Factor Above TA = 25°C(2) | 16.7 | 8.5 | 7.6 | 6.2 | mW/°C | |
Power Rating: TA≤ 25°C | 2094 | 1071 | 950 | 774 | mW | |
Power Rating: TA = 70°C | 1342 | 688 | 608 | 496 | ||
Power Rating: TA = 85°C | 1089 | 556 | 494 | 402 |
PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
|VOD| | Differential output voltage magnitude | RL = 100 Ω, See Figure 9 and Figure 10 |
247 | 340 | 454 | mV | |
Δ|VOD| | Change in differential output voltage magnitude between logic states | –50 | 50 | ||||
VOC(SS) | Steady-state common-mode output voltage | See Figure 11 | 1.125 | 1.375 | V | ||
ΔVOC(SS) | Change in steady-state common-mode output voltage between logic states | –50 | 50 | mV | |||
VOC(PP) | Peak-to-peak common-mode output voltage | 50 | 150 | mV | |||
ICC | Supply current | 'LVDS387 | Enabled, RL = 100 Ω, VIN = 0.8 V or 2 V |
85 | 95 | mA | |
'LVDS389 | 50 | 70 | |||||
'LVDS391 | 20 | 26 | |||||
'LVDS387 | Disabled, VIN = 0 V or VCC |
0.5 | 1.5 | ||||
'LVDS389 | 0.5 | 1.5 | |||||
'LVDS391 | 0.5 | 1.3 | |||||
IIH | High-level input current | VIH = 2 V | 3 | 20 | µA | ||
IIL | Low-level input current | VIL = 0.8 V | 2 | 10 | µA | ||
IOS | Short-circuit output current | VOY or VOZ = 0 V | ±24 | mA | |||
VOD = 0 V | ±12 | mA | |||||
IOZ | High-impedance output current | VO = 0 V or VCC | ±1 | µA | |||
IO(OFF) | Power-off output current | VCC = 1.5 V, VO = 2.4 V | ±1 | µA | |||
CIN | Input capacitance | VI = 0.4sin(4E6πt) + 0.5 V | 5 | pF | |||
CO | Output capacitance | VI = 0.4sin(4E6πt) + 0.5 V, Disabled | 9.4 | pF |
PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | |
---|---|---|---|---|---|---|
tPLH | Propagation delay time, low-to-high-level output | RL = 100 Ω, CL = 10 pF, See Figure 12 |
0.9 | 1.7 | 2.9 | ns |
tPHL | Propagation delay time, high-to-low-level output | 0.9 | 1.6 | 2.9 | ns | |
tr | Differential output signal rise time | 0.4 | 0.8 | 1 | ns | |
tf | Differential output signal fall time | 0.4 | 0.8 | 1 | ns | |
tsk(p) | Pulse skew (|tPHL – tPLH|) | 150 | 500 | ps | ||
tsk(o) | Output skew(2) | 80 | 150 | ps | ||
tsk(pp) | Part-to-part skew(3) | 1.5 | ns | |||
tPZH | Propagation delay time, high-impedance-to-high-level output | See Figure 13 | 6.4 | 15 | ns | |
tPZL | Propagation delay time, high-impedance-to-low-level output | 5.9 | 15 | ns | ||
tPHZ | Propagation delay time, high-level-to-high-impedance output | 3.5 | 15 | ns | ||
tPLZ | Propagation delay time, low-level-to-high-impedance output | 4.5 | 15 | ns |