SLLSE15A July   2011  – November 2015 SN65LVDS4

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Receiver Electrical Characteristics: VCC = 2.5 V
    6. 6.6 Receiver Electrical Characteristics: VCC = 1.8 V
    7. 6.7 Receiver Switching Characteristics: VCC = 2.5 V
    8. 6.8 Receiver Switching Characteristics: VCC = 1.8 V
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Failsafe
        1. 8.3.1.1 R1 and R3 Calculation With VCC = 1.8 V
        2. 8.3.1.2 R1 and R3 Calculation With VCC = 2.5 V
    4. 8.4 Device Functional Modes
      1. 8.4.1 Maximum Input Voltage, VIN(max)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Receiver Bypass Capacitance
        2. 9.2.2.2 Receiver Input Voltage
        3. 9.2.2.3 Interconnecting Media
        4. 9.2.2.4 PCB Transmission Lines
        5. 9.2.2.5 Termination Resistor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Microstrip vs. Stripline Topologies
      2. 11.1.2 Dielectric Type and Board Construction
      3. 11.1.3 Recommended Stack Layout
      4. 11.1.4 Separation Between Traces
      5. 11.1.5 Crosstalk and Ground Bounce Minimization
      6. 11.1.6 Decoupling
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The SN65LVDS4 device is a single-channel LVDS line receiver. It operates from two power supplies, VCC which is the core power supply and VDD which is the output drive power supply. The input signal to the SN65LVDS4 is a differential LVDS signal. The output of the device can be 3.3V LVTTL, 2.5V LVCMOS or 1.8V LVCMOS. This LVDS receiver requires ±50 mV of input signal to determine the correct state of the received signal. The SN65LVDS4 can be used in a point-to-point system or in a multidrop system.

8.2 Functional Block Diagram

SN65LVDS4 fbd_LSSE15.png

8.3 Feature Description

8.3.1 Failsafe

One of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that the output logic state can be indeterminate when the differential input voltage is between –50 mV and 50 mV and within its recommended input common-mode voltage range.

Open circuit means that there is little or no input current to the receiver from the data line itself. This could be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, TI recommends to have an external failsafe solution as shown in Figure 20. In the external failsafe solution, the A side is pulled to VCC via a weak pullup resistor and the B side is pulled down via a weak pulldown resistor. This creates a voltage offset and prevents the receiver from switching based on noise.

SN65LVDS4 ai-op-cir_LLSE15.gif Figure 20. Open-Circuit Failsafe of the LVDS Receiver

8.3.1.1 R1 and R3 Calculation With VCC = 1.8 V

  • Assume that an external failsafe bias of 25 mV is desired
  • Bias current in this case is = 25 mV/100 Ω = 250 µA
  • Next, determine the total resistance from VCC to ground = 1.8 V/250 µA = 7.2 kΩ
  • Keeping the common mode bias of 1.25 V to the receiver, the value of R3 = 1.25 V/250 µA = 5 kΩ
  • Thus, R1 = 2.2 kΩ

8.3.1.2 R1 and R3 Calculation With VCC = 2.5 V

  • Assume that an external failsafe bias of 25 mV is desired
  • Bias current in this case is = 25 mV/100 Ω = 250 µA
  • Next, determine the total resistance from VCC to ground = 2.5 V/250 µA = 10 kΩ
  • Keeping the common mode bias of 1.25 V to the receiver, the value of R3 = 1.25 V/250 µA = 5 kΩ
  • Thus, R1 = 5 kΩ

8.4 Device Functional Modes

8.4.1 Maximum Input Voltage, VIN(max)

SN65LVDS4 Vcc_LLSE15.gif Figure 21. Maximum Input Voltage Combination Allowed

Table 1. Function Table

INPUTS OUTPUT(1)
VID = VA – VB R
VID ≥ 50 mV H
VID ≤ –50 mV L
(1) H = high level, L = low level, ? = indeterminate
SN65LVDS4 RecEqIO_LLSE15.gif Figure 22. Receiver Equivalent Input and Output Schematic Diagrams