SLLSE15A July   2011  – November 2015 SN65LVDS4

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Receiver Electrical Characteristics: VCC = 2.5 V
    6. 6.6 Receiver Electrical Characteristics: VCC = 1.8 V
    7. 6.7 Receiver Switching Characteristics: VCC = 2.5 V
    8. 6.8 Receiver Switching Characteristics: VCC = 1.8 V
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Failsafe
        1. 8.3.1.1 R1 and R3 Calculation With VCC = 1.8 V
        2. 8.3.1.2 R1 and R3 Calculation With VCC = 2.5 V
    4. 8.4 Device Functional Modes
      1. 8.4.1 Maximum Input Voltage, VIN(max)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Receiver Bypass Capacitance
        2. 9.2.2.2 Receiver Input Voltage
        3. 9.2.2.3 Interconnecting Media
        4. 9.2.2.4 PCB Transmission Lines
        5. 9.2.2.5 Termination Resistor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Microstrip vs. Stripline Topologies
      2. 11.1.2 Dielectric Type and Board Construction
      3. 11.1.3 Recommended Stack Layout
      4. 11.1.4 Separation Between Traces
      5. 11.1.5 Crosstalk and Ground Bounce Minimization
      6. 11.1.6 Decoupling
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage range, VCC (2) –0.5 4 V
Receiver output voltage logic level and driver input voltage logic level supply, VDD –0.5 4 V
Input voltage range, VI (A or B) –0.5 VCC + 0.3 V
Output voltage, VO (R) –0.5 VDD + 0.3 V
Differential input voltage magnitude, |VID| 1 V
Receiver output current, IO –12 12 mA
Continuous total power dissipation, PD See Thermal Information
Storage temperature (non operating) –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) All pins 2000 V
Bus pins (A, B, Y, Z) 2000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) 500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC1.8 Core supply voltage 1.62 1.8 1.98 V
VCC2.5 Core supply voltage 2.25 2.5 2.75 V
VDD1.8 Output drive voltage 1.62 1.8 1.98 V
VDD2.5 Output drive voltage 2.25 2.5 2.75 V
VDD3.3 Output drive voltage 3 3.3 3.6 V
TA Operating free-air temperature –40 85 °C
|VID| Magnitude of differential input voltage 0.15 0.6 V
fop Operating frequency range 10 250 MHz
|VINMAX| Input voltage (any combination of input or common-mode voltage) See (1)Maximum Input Voltage, VIN(max). 0 VCC V
(1) Any combination of input or common-mode voltage should not be below 0 V or above VCC.

6.4 Thermal Information

THERMAL METRIC(1) SN65LVDS4 UNIT
RSE (UQFN)
10 PINS
RθJA Junction-to-ambient thermal resistance 171.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 60.7 °C/W
RθJB Junction-to-board thermal resistance 71.4 °C/W
ψJT Junction-to-top characterization parameter 0.8 °C/W
ψJB Junction-to-board characterization parameter 64.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Receiver Electrical Characteristics: VCC = 2.5 V

over recommended operating conditions, VCC = 2.5 V, VID = 150 mV–600 mV, VCM = VID/2 to VCC – VID/2 V, 10 pF load (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN(2) TYP(1) MAX UNIT
VITH+ Positive-going differential input voltage threshold See Figure 17, VCC1.8 , VCC2.5 50 mV
VITH– Negative-going differential input voltage threshold See Figure 17, VCC1.8 , VCC2.5 –50 mV
VOH High-level output voltage VDD = 3.3 V, IOH = –8 mA VDD – 0.25 V
VDD = 2.5 V, IOH = –6 mA VDD – 0.25
VDD = 1.8 V, IOH = –4 mA VDD – 0.25
VOL Low-level output voltage VDD = 3.3 V, IOL = 8 mA 0.25 V
VDD = 2.5 V, IOL = 6 mA 0.25
VDD = 1.8 V, IOL = 4 mA 0.25
Pstatic Static power No load, steady state, VDD = 3.3 V, VID+ 22 28 mW
No load, steady state, VDD = 2.5 V, VID+ 20 25
CI Input capacitance VI = 0.4 sin(4E6πt) + 0.5 V 4 pF
CO Output capacitance VI = 0.4 sin(4E6πt) + 0.5 V 4 pF
(1) All typical values are at 25°C .
(2) The algebraic convention, in which the least positive (most negative) limit is designated as a minimum, is used in this data sheet.

6.6 Receiver Electrical Characteristics: VCC = 1.8 V

over recommended operating conditions, VCC = 1.8 V, VID = 150 mV–600 mV, VCM = VID/2 to VCC – VID/2 V, 10 pF load (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN(2) TYP(1) MAX UNIT
VITH+ Positive-going differential input voltage threshold See Figure 17, VCC1.8 , VCC2.5 50 mV
VITH– Negative-going differential input voltage threshold See Figure 17, VCC1.8 , VCC2.5 –50 mV
VOH High-level output voltage VDD = 3.3 V, IOH = –8 mA VDD – 0.25 V
VDD = 2.5 V, IOH = –6 mA VDD – 0.25
VDD = 1.8 V, IOH = –4 mA VDD – 0.25
VOL Low-level output voltage VDD = 3.3 V, IOL = 8 mA 0.25 V
VDD = 2.5 V, IOL = 6 mA 0.25
VDD = 1.8 V, IOL = 4 mA 0.25
Pstatic Static power No load, steady state, VDD = 3.3 V, VID+ 18 21 mW
No load, steady state, VDD = 2.5 V, VID+ 16 19
No load, steady state, VDD = 1.8 V, VID+ 13 16
CI Input capacitance VI = 0.4 sin(4E6πt) + 0.5 V 4 pF
CO Output capacitance VI = 0.4 sin(4E6πt) + 0.5 V 4 pF

6.7 Receiver Switching Characteristics: VCC = 2.5 V

over recommended operating conditions, VCC = 2.5 V, VID = 150 mV–600 mV, VCM = VID/2 to VCC – VID/2 V, 10 pF load (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
tPLH Propagation delay time, low-to-high-level output CL = 10 pF,
See Figure 19 		2.5 3.3 ns
tPHL Propagation delay time, high-to-low-level output 2.5 3.3 ns
tsk(p) Pulse skew (|tpHL – tpLH|)(2) 240 ps
tr Output signal rise time VDD = 3.3 V 550 ps
VDD = 2.5 V 600
tf Output signal fall time VDD = 3.3 V 550 ps
VDD = 2.5 V 600
tjit Residual jitter added Carrier frequency = 122.8 MHz, input signal amplitude = 500 mVpp sine wave, integration bandwidth for rms jitter = 20 khz-20 MHz, VDD = 2.5 V 370 fs
(1) All typical values are at 25°C.
(2) tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.

6.8 Receiver Switching Characteristics: VCC = 1.8 V

over recommended operating conditions, VCC = 1.8 V, VID = 150 mV–600 mV, VCM = VID/2 to VCC – VID/2 V, 10 pF load (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
tPLH Propagation delay time, low-to-high-level output CL = 10 pF,
See Figure 19 		3.2 3.8 ns
tPHL Propagation delay time, high-to-low-level output 3.2 3.8 ns
tsk(p) Pulse skew (|tpHL – tpLH|)(2) 240 ps
tr Output signal rise time VDD = 3.3 V 550 ps
VDD = 2.5 V 600
VDD = 1.8 V 750
tf Output signal fall time VDD = 3.3 V 550 ps
VDD = 2.5 V 600
VDD = 1.8 V 750
tjit Residual jitter added Carrier frequency = 122.8 MHz, input signal amplitude = 500 mVpp sine wave, integration bandwidth for rms jitter = 20 khz-20 MHz, VDD = 1.8 V 370 fs

6.9 Typical Characteristics

VICM = 1.2 V, VID = 300 mV, CL = 10 pF, input rise time and fall time = 1 ns, input frequency = 250 MHz, 50% duty cycle, TA = 25°C, unless otherwise noted
SN65LVDS4 G001_LLSE15.png Figure 1. High-Level Output Voltage vs. High-Level Output Current
SN65LVDS4 G003_LLSE15.png Figure 3.  High- to Low-Level Propagation Delay Time vs. Free-Air Temperature
SN65LVDS4 G005_LLSE15.png Figure 5. Rise Time vs. Capacitive Load
SN65LVDS4 G007_LLSE15.png Figure 7. Supply Current vs. Frequency
SN65LVDS4 G009_LLSE15.png Figure 9. Pulse Skew vs. Temperature
SN65LVDS4 G011_LLSE15.png Figure 11. Pulse Skew vs. Differential Input Voltage
SN65LVDS4 G013_LLSE15.png Figure 13. Propagation Delay, Low-to-High vs. Differential Input Voltage
SN65LVDS4 G015_LLSE15.png Figure 15. Propagation Delay, High-to-Low vs. Differential Input Voltage
SN65LVDS4 G002_LLSE15.png Figure 2. Low-Level Output Voltage vs. Low-Level Output Current
SN65LVDS4 G004_LLSE15.png Figure 4. Low- to High-Level Propagation Delay Time vs. Free-Air Temperature
SN65LVDS4 G006_LLSE15.png Figure 6. Fall Time vs. Capacitive Load
SN65LVDS4 G008_LLSE15.png Figure 8. Supply Current vs. Temperature
SN65LVDS4 G010_LLSE15.png Figure 10. Pulse Skew vs. Common-Mode Voltage
SN65LVDS4 G012_LLSE15.png Figure 12. Propagation Delay, Low-to-High vs. Common-Mode Voltage
SN65LVDS4 G014_LLSE15.png Figure 14. Propagation Delay, High-to-Low vs. Common-Mode Voltage
SN65LVDS4 G016_LLSE15.png Figure 16. Power vs. Frequency