SLLSEE8B September   2013  – September 2014 SN65LVDS822

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Electrical Characteristics
    6. 7.6 Power Supply Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Test Patterns
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Unused LVDS Data Lanes
      2. 9.3.2 Tying CMOS Inputs With Resistors
    4. 9.4 Device Functional Modes
      1. 9.4.1 Active Modes
        1. 9.4.1.1 4-Lanes 7-Bit Mode
        2. 9.4.1.2 2-Lanes 14-Bit Mode
      2. 9.4.2 Low-Power Modes
        1. 9.4.2.1 Standby Mode
        2. 9.4.2.2 Shutdown Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Color Bit Mapping
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Power Supply
        2. 10.2.2.2 CMOS Output Bus Connector
        3. 10.2.2.3 Power-Up Sequence
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Decoupling Capacitor Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Trademarks
    2. 13.2 Electrostatic Discharge Caution
    3. 13.3 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Description (Continued)

A clock frequency range of 4 MHz to 54 MHz is supported in the standard 7x mode, which is to be used with LVDS data rates of 28 Mbps to 378 Mbps. The 14x mode supports 4 MHz to 27 MHz, for LVDS data rates of 56Mbps to 378 Mbps. The LVDS clock frequency always matches the CMOS output clock frequency. DC common mode voltage is monitored on clock line for normal operation. The device is designed to support resolutions as low as 1/16th VGA (160 × 120), and as high as 1024 × 600, with 60 frames per second and 24-bit color.

The SN65LVDS822 features an automatic low-power standby mode, activated when the LVDS clock is disabled. The device enters an even lower-power shutdown mode with a low voltage applied to pin SHTDN#. In both low-power modes, all CMOS outputs drive low. All input pins have fail-safe protection that prevents damage from occurring before power supply voltages are high and stable.

The SN65LVDS822 is packaged in a 48-pin 7-mm x 7-mm Plastic Quad Flatpack No-Lead (QFN) with a 0.5-mm pin pitch, and operates through an industrial ambient temperature range of –40°C to 85°C.