SLLSEE8B September   2013  – September 2014 SN65LVDS822

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Electrical Characteristics
    6. 7.6 Power Supply Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Test Patterns
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Unused LVDS Data Lanes
      2. 9.3.2 Tying CMOS Inputs With Resistors
    4. 9.4 Device Functional Modes
      1. 9.4.1 Active Modes
        1. 9.4.1.1 4-Lanes 7-Bit Mode
        2. 9.4.1.2 2-Lanes 14-Bit Mode
      2. 9.4.2 Low-Power Modes
        1. 9.4.2.1 Standby Mode
        2. 9.4.2.2 Shutdown Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Color Bit Mapping
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Power Supply
        2. 10.2.2.2 CMOS Output Bus Connector
        3. 10.2.2.3 Power-Up Sequence
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Decoupling Capacitor Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Trademarks
    2. 13.2 Electrostatic Discharge Caution
    3. 13.3 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

RGZ PACKAGE
(TOP VIEW)
SWAP Pin = Low or Floating
po_rgz_low_llsee8.gif
RGZ PACKAGE
(TOP VIEW)
SWAP Pin = High
po_rgz_high_llsee8.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
A0P, A0N 26, 25 LVDS Input LVDS Data Lane 0
A1P, A1N 28, 27 LVDS Data Lane 1
A2P, A2N 30, 29 LVDS Data Lane 2
A3P, A3N 34, 33 LVDS Data Lane 3
CLKP, CLKN 32, 31 LVDS Clock
(SWAP = L / H) CMOS Output Data bus output
D0 22 / 38
D1 21 / 39
D2 20 / 40
D3 19 / 42
D4 18 / 46
D5 16 / 47
D6 13 / 2
D7 12 / 3
D8 11 / 4
D9 10 / 5
D10 9 / 7
D11 8 / 8
D12 4 / 11
D13 3 / 12
D14 2 / 13
D15 1 / 14
D16 48 / 15
D17 47 / 16
D18 40 / 20
D19 39 / 21
D20 38 / 22
D21 15 / 48
D22 14 / 1
D23 7 / 9
D24 5 / 10
D25 46 / 18
D26 42 / 19
CLKOUT 41 Clock output for the data bus
SWAP 45 CMOS Input Selects the CMOS output pinout, and also controls differential input termination.
Low – Default pinout, RID connected
Floating – Default pinout, RID disconnected (requires external termination)
High – Swapped pinout, RID connected
MODE14 36 Sets the number of LVDS serial bits per lane per clock period.
Low – 7 bits (see Figure 16)
High – 14 bits; only lanes A0 and A2 are used (see Figure 17)
CLKPOL 23 CLKOUT polarity
Low – D[26:0] is valid during the CLKOUT falling edge
Floating – Reserved; do not use
High – D[26:0] is valid during the CLKOUT rising edge
SHTDN# 37 Shutdown Mode; Active-Low
SLEW 35 Sets the CMOS output slew rate
Low – Slowest rise/fall time
Floating – Medium rise/fall time
High – Fastest rise/fall time
VDD 24, 44 Power Supply Main power supply; 3.3 V
VDDIO 6, 17, 43 Power supply for CMOS outputs; 1.8 V to 3.3 V
GND Thermal Pad Reference Ground