DATA SHEET
SN65LVDS93A-Q1 FlatLink™ Transmitter
1 Features
- AEC-Q100 Qualified with:
- LVDS Display Series Interfaces Directly to LCD Display Panels With Integrated LVDS
- Package: 14-mm x 6.1-mm TSSOP
- 1.8-V Up to 3.3-V Tolerant Data Inputs to Connect Directly to Low-Power, Low-Voltage Application and Graphic Processors
- Transfer Rate up to 135 Mpps (Mega Pixel Per Second); Pixel Clock Frequency Range 10 MHz to 135 MHz
- Suited for Display Resolutions Ranging From HVGA up to HD With Low EMI
- Operates From a Single 3.3-V Supply and 170 mW (Typical) at 75 MHz
- 28 Data Channels Plus Clock in Low-Voltage TTL to 4 Data Channels Plus Clock Out Low-Voltage Differential
- Consumes Less Than 1 mW When Disabled
- Selectable Rising or Falling Clock Edge Triggered Inputs
- Support Spread Spectrum Clocking (SSC)
- Compatible with all OMAP™ 2x, OMAP™ 3x, and DaVinci™ Application Processors
2 Applications
- LCD Display Panel Driver
- UMPC and Netbook PC
- Digital Picture Frame
3 Description
The SN65LVDS93A-Q1 FlatLink™ transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS94 and LCD panels with integrated LVDS receiver.
When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.
The SN65LVDS93A-Q1 requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a low-level input, and the possible use of the Shutdown/Clear (SHTDN). SHTDN is an active-low input to inhibit the clock, and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers to a low-level.
The SN65LVDS93A-Q1 is characterized for operation over ambient air temperatures of –40°C to 85°C.
Device Information(1)
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| SN65LVDS93A-Q1 | TSSOP (56) | 14.00 mm x 6.10 mm |
- For all available packages, see the orderable addendum at the end of the datasheet.
Simplified Schematic
4 Revision History
Changes from A Revision (February 2015) to B Revision
- Changed "Toggle LVDS83B" To "Toggle SN65LVDS93A-Q1" in item 4 in the Power Up Sequence sectionGo
- Changed "this allows the LVDS83B" To "this allows the SN65LVDS93A-Q1" in item 5 in the Power Up Sequence sectionGo
Changes from * Revision (February 2015) to A Revision
5 Pin Configuration and Functions
56-PIN
DGG PACKAGE
(TOP VIEW)
Pin Functions
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| CLKIN | 31 | CMOS IN with pulldn | Input pixel clock; rising or falling clock polarity is selectable by Control input CLKSEL. |
| CLKOUTP, CLKOUTM |
39 40 |
LVDS Out | Differential LVDS pixel clock output. Output is high-impedance when SHTDN is pulled low (de-asserted). |
| CLKSEL | 17 | CMOS IN with pulldn | Selects between rising edge input clock trigger (CLKSEL = VIH) and falling edge input clock trigger (CLKSEL = VIL). |
| D5, D6, D7, D8 D9, D10, D11, D12 D13, D14, D15, D16 D17, D18, D19, D20 D21, D22, D23, D24 D25, D26, D27 D0, D1, D2, D3, D4 |
2, 3, 4, 6 7, 8, 10, 11 12, 14, 15 , 16 18, 19, 20, 22 23, 24, 25, 27 28, 30, 50 51, 52, 54, 55, 56 |
CMOS IN with pulldn | Data inputs; supports 1.8 V to 3.3 V input voltage selectable by VDD supply. To connect a graphic source successfully to a display, the bit assignment of D[27:0] is critical (and not necessarily intuitive). For input bit assignment see Figure 15 to Figure 18 for details. Note: if application only requires 18-bit color, connect unused inputs D5, D10, D11, D16, D17, D23, and D27 to GND. |
| GND | 5, 13, 21, 29, 33, 35, 36, 43, 49, 53 | Power Supply(1) | Supply ground for VCC, IOVCC, LVDSVCC, and PLLVCC. |
| IOVCC | 1, 26 | Power Supply(1) | I/O supply reference voltage (1.8 V up to 3.3 V matching the GPU data output signal swing) |
| LVDSVCC | 44 | Power Supply(1) | 3.3 V LVDS output analog supply |
| PLLVCC | 34 | Power Supply(1) | 3.3 V PLL analog supply |
| SHTDN | 32 | CMOS IN with pulldn | Device shut down; pull low (de-assert) to shut down the device (low power, resets all registers) and high (assert) for normal operation. |
| VCC | 9 | Power Supply(1) | 3.3 V digital supply voltage |
| Y0P, Y0M Y1P, Y1M Y2P, Y2M |
47, 48 45, 46 41, 42 |
LVDS Out | Differential LVDS data outputs. Outputs are high-impedance when SHTDN is pulled low (de-asserted) |
| Y3P, Y3M | 37, 38 | LVDS Out | Differential LVDS Data outputs. Output is high-impedance when SHTDN is pulled low (de-asserted). Note: if the application only requires 18-bit color, this output can be left open. |
(1) For a multilayer pcb, it is recommended to keep one common GND layer underneath the device and connect all ground terminals directly to this plane.
6 Specifications
6.1 Absolute Maximum Ratings(1)
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Supply voltage range, VCC, IOVCC, LVDSVCC, PLLVCC(2) | –0.5 | 4 | V | |
| Voltage range at any output terminal | –0.5 | VCC + 0.5 | V | |
| Voltage range at any input terminal | –0.5 | IOVCC + 0.5 | V | |
| Continuous power dissipation | See Thermal Information | |||
| Storage temperature, Tstg | –65 | 150 | °C | |
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
(2) All voltages are with respect to the GND terminals.
6.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q200-002(1) | ±4000 | V |
| Charged-device model (CDM), per AEC Q100-011 | ±1500 | |||
(1) AEC Q200-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)| PARAMETER | MIN | NOM | MAX | UNIT | |
|---|---|---|---|---|---|
| Supply voltage, VCC | 3 | 3.3 | 3.6 | V | |
| LVDS output Supply voltage, LVDSVCC | 3 | 3.3 | 3.6 | ||
| PLL analog supply voltage, PLLVCC | 3 | 3.3 | 3.6 | ||
| IO input reference supply voltage, IOVCC | 1.62 | 1.8 / 2.5 / 3.3 | 3.6 | ||
| Power supply noise on any VCC terminal | 0.1 | ||||
| High-level input voltage, VIH | IOVCC = 1.8 V | IOVCC/2 + 0.3 V | V | ||
| IOVCC = 2.5 V | IOVCC/2 + 0.4 V | ||||
| IOVCC = 3.3 V | IOVCC/2 + 0.5 V | ||||
| Low-level input voltage, VIL | IOVCC = 1.8 V | IOVCC/2 - 0.3 V | V | ||
| IOVCC = 2.5 V | IOVCC/2 - 0.4 V | ||||
| IOVCC = 3.3 V | IOVCC/2 - 0.5 V | ||||
| Differential load impedance, ZL | 90 | 132 | Ω | ||
| Operating free-air temperature, TA | –40 | 85 | °C | ||
| Virtual junction temperature, TJ | 105 | °C | |||
6.4 Thermal Information
| THERMAL METRIC(1) | DGG | UNIT | |
|---|---|---|---|
| 56 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 63.4 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 15.9 | |
| RθJB | Junction-to-board thermal resistance | 32.5 | |
| ψJT | Junction-to-top characterization parameter | 0.4 | |
| ψJB | Junction-to-board characterization parameter | 32.2 | |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | |
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | |
|---|---|---|---|---|---|---|
| VT | Input voltage threshold | RL = 100Ω, See Figure 7 | IOVCC/2 | V | ||
| |VOD| | Differential steady-state output voltage magnitude | 250 | 450 | mV | ||
| Δ|VOD| | Change in the steady-state differential output voltage magnitude between opposite binary states | 1 | 35 | mV | ||
| VOC(SS) | Steady-state common-mode output voltage | See Figure 7
tR/F (Dx, CLKin) = 1ns |
1.125 | 1.375 | V | |
| VOC(PP) | Peak-to-peak common-mode output voltage | 35 | mV | |||
| IIH | High-level input current | VIH = IOVCC | 25 | μA | ||
| IIL | Low-level input current | VIL = 0 V | ±10 | μA | ||
| IOS | Short-circuit output current | VOY = 0 V | ±24 | mA | ||
| VOD = 0 V | ±12 | mA | ||||
| IOZ | High-impedance state output current | VO = 0 V to VCC | ±20 | μA | ||
| Rpdn | Input pull-down integrated resistor on all inputs (Dx, CLKSEL, SHTDN, CLKIN) | IOVCC = 1.8 V | 200 | kΩ | ||
| IOVCC = 3.3 V | 100 | |||||
| IQ | Quiescent current (average) | disabled, all inputs at GND; SHTDN = VIL |
2 | 100 | μA | |
| ICC | Supply current (average) | SHTDN = VIH, RL = 100Ω (5 places), grayscale pattern (Figure 8) VCC = 3.3 V, fCLK = 75 MHz |
||||
| I(VCC) + I(PLLVCC) + I(LVDSVCC) | 51.9 | mA | ||||
| I(IOVCC) with IOVCC = 3.3 V | 0.4 | |||||
| I(IOVCC) with IOVCC = 1.8 V | 0.1 | |||||
| SHTDN = VIH, RL = 100Ω (5 places), 50% transition density pattern (Figure 8), VCC = 3.3 V, fCLK = 75 MHz |
||||||
| I(VCC) + I(PLLVCC) + I(LVDSVCC) | 53.3 | mA | ||||
| I(IOVCC) with IOVCC = 3.3 V | 0.6 | |||||
| I(IOVCC) with IOVCC = 1.8 V | 0.2 | |||||
| SHTDN = VIH, RL = 100Ω (5 places), worst-case pattern (Figure 9), VCC = 3.6 V, fCLK = 75 MHz |
||||||
| I(VCC) + I(PLLVCC) + I(LVDSVCC) | 63.7 | mA | ||||
| I(IOVCC) with IOVCC = 3.3 V | 1.3 | |||||
| I(IOVCC) with IOVCC = 1.8 V | 0.5 | |||||
| SHTDN = VIH, RL = 100Ω (5 places), worst-case pattern (Figure 9), fCLK = 100 MHz |
||||||
| I(VCC) + I(PLLVCC) + I(LVDSVCC) | 81.6 | mA | ||||
| I(IOVCC) with IOVCC = 3.6 V | 1.6 | |||||
| I(IOVCC) with IOVCC = 1.8 V | 0.6 | |||||
| SHTDN = VIH, RL = 100Ω (5 places), worst-case pattern (Figure 9), fCLK = 135 MHz |
||||||
| I(VCC) + I(PLLVCC) + I(LVDSVCC) | 102.2 | mA | ||||
| I(IOVCC) with IOVCC = 3.6 V | 2.1 | |||||
| I(IOVCC) with IOVCC = 1.8 V | 0.8 | |||||
| CI | Input capacitance | 2 | pF | |||
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
6.6 Timing Requirements
| PARAMETER | MIN | MAX | UNIT | |
|---|---|---|---|---|
| Input clock period, tc | 7.4 | 100 | ns | |
| Input clock modulation | with modulation frequency 30 kHz | 8% | ||
| with modulation frequency 50 kHz | 6% | |||
| High-level input clock pulse width duration, tw | 0.4 tc | 0.6 tc | ns | |
| Input signal transition time, tt | 3 | ns | ||
| Data set up time, D0 through D27 before CLKIN (See Figure 6) | 2 | ns | ||
| Data hold time, D0 through D27 after CLKIN | 0.8 | ns | ||
Figure 1. Typical SN65LVDS93A-Q1 Load and Shift Sequences
Figure 2. Equivalent Input and Output Schematic Diagrams
6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | |
|---|---|---|---|---|---|---|
| t0 | Delay time, CLKOUT↑ after Yn valid (serial bit position 0, equal D1, D9, D20, D5) | See Figure 10, tC = 10ns, |Input clock jitter| < 25ps (2) |
-0.1 | 0 | 0.1 | ns |
| t1 | Delay time, CLKOUT↑ after Yn valid (serial bit position 1, equal D0, D8, D19, D27) | 1/7 tc - 0.1 | 1/7 tc + 0.1 | ns | ||
| t2 | Delay time, CLKOUT↑ after Yn valid (serial bit position 2, equal D7, D18, D26. D23) | 2/7 tc - 0.1 | 2/7 tc + 0.1 | ns | ||
| t3 | Delay time, CLKOUT↑ after Yn valid (serial bit position 3; equal D6, D15, D25, D17) | 3/7 tc - 0.1 | 3/7 tc + 0.1 | ns | ||
| t4 | Delay time, CLKOUT↑ after Yn valid (serial bit position 4, equal D4, D14, D24, D16) | 4/7 tc - 0.1 | 4/7 tc + 0.1 | ns | ||
| t5 | Delay time, CLKOUT↑ after Yn valid (serial bit position 5, equal D3, D13, D22, D11) | 5/7 tc - 0.1 | 5/7 tc + 0.1 | ns | ||
| t6 | Delay time, CLKOUT↑ after Yn valid (serial bit position 6, equal D2, D12, D21, D10) | 6/7 tc - 0.1 | 6/7 tc + 0.1 | ns | ||
| tc(o) | Output clock period | tc | ns | |||
| Δtc(o) | Output clock cycle-to-cycle jitter (3) | tC = 10ns; clean reference clock, see Figure 11 | ±26 | ps | ||
| tC = 10ns with 0.05UI added noise modulated at 3MHz, see Figure 11 | ±44 | |||||
| tC = 7.4ns; clean reference clock, see Figure 11 | ±35 | |||||
| tC = 7.4ns with 0.05UI added noise modulated at 3MHz, see Figure 11 | ±42 | |||||
| tw | High-level output clock pulse duration | 4/7 tc | ns | |||
| tr/f | Differential output voltage transition time (tr or tf) | See Figure 7 | 225 | 500 | ps | |
| ten | Enable time, SHTDN↑ to phase lock (Yn valid) | f(clk) = 135 MHz, See Figure 12 | 6 | µs | ||
| tdis | Disable time, SHTDN↓ to off-state (CLKOUT high-impedance) | f(clk) = 135 MHz, See Figure 13 | 7 | ns | ||
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) |Input clock jitter| is the magnitude of the change in the input clock period.
(3) The output clock cycle-to-cycle jitter is the largest recorded change in the output clock period from one cycle to the next cycle observed over 15,000 cycles.Tektronix TDSJIT3 Jitter Analysis software was used to derive the maximum and minimum jitter value.
6.8 Typical Characteristics
| Total Device Current (Using Grayscale pattern) Over Pixel Clock Frequency |
| Clock Signal = 135 MHz | ||
| CLK Frequency During Test = 100 MHz | ||
7 Parameter Measurement Information
All input timing is defined at IOVDD / 2 on an input signal with a 10% to 90% rise or fall time of less than 3 ns. CLKSEL = 0 V.
Figure 6. Set Up and Hold Time Definition
Figure 7. Test Load and Voltage Definitions for LVDS Outputs
The 16 grayscale test pattern test device power consumption for a typical display pattern.
Figure 8. 16 Grayscale Test Pattern
The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs.
Figure 9. Worst-Case Power Test Pattern
CLKOUT is shown with CLKSEL at high-level.
CLKIN polarity depends on CLKSEL input level.
Figure 10. SN65LVDS93A-Q1 Timing Definitions
CLKIN polarity depends on CLKSEL input level.
Figure 11. Output Clock Jitter Test Set Up
Figure 12. Enable Time Waveforms
Figure 13. Disable Time Waveforms
