SLLSEM1B February 2015 – April 2015 SN65LVDS93A-Q1
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
This section describes the power up sequence, provides information on device connectivity to various GPU and LCD display panels, and offers a PCB routing example.
DESIGN PARAMETER | EXAMPLE VALUE |
---|---|
VCC | 3.3 V |
VCCIO | 1.8 V |
CLKIN | Falling edge |
SHTDN# | High |
Format | 18-bit GPU to 24-bit LCD |
The SN65LVDS93A-Q1 does not require a specific power up sequence.
It is permitted to power up IOVCC while VCC, VCCPLL, and VCCLVDS remain powered down and connected to GND. The input level of the SHTDN during this time does not matter as only the input stage is powered up while all other device blocks are still powered down.
It is also permitted to power up all 3.3V power domains while IOVCC is still powered down to GND. The device will not suffer damage. However, in this case, all the I/Os are detected as logic HIGH, regardless of their true input voltage level. Hence, connecting SHTDN to GND will still be interpreted as a logic HIGH; the LVDS output stage will turn on. The power consumption in this condition is significantly higher than standby mode, but still lower than normal mode.
The user experience can be impacted by the way a system powers up and powers down an LCD screen. The following sequence is recommended:
Power up sequence (SN65LVDS93A-Q1 SHTDN input initially low):
Power Down sequence (SN65LVDS93A-Q1 SHTDN input initially high):
While there is no formal industry standardized specification for the input interface of LVDS LCD panels, the industry has aligned over the years on a certain data format (bit order). Figure 15 through Figure 18 show how each signal should be connected from the graphic source through the SN65LVDS93A-Q1 input, output and LVDS LCD panel input. Detailed notes are provided with each figure.