SLLS992B August   2009  – March 2015 SN65LVDS93A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 TTL Input Data
      2. 9.3.2 LVDS Output Data
    4. 9.4 Device Functional Modes
      1. 9.4.1 Input Clock Edge
      2. 9.4.2 Low Power Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Power
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Signal Connectivity
        2. 10.2.2.2 PCB Routing
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Board Stackup
      2. 12.1.2 Power and Ground Planes
      3. 12.1.3 Traces, Vias, and Other PCB Components
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings(1)

MIN MAX UNIT
Supply voltage, VCC, IOVCC, LVDSVCC, PLLVCC(2) –0.5 4 V
Voltage at any output terminal –0.5 VCC + 0.5 V
Voltage at any input terminal –0.5 IOVCC + 0.5 V
Continuous power dissipation See Thermal Information
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to the GND terminals.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±5000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN NOM MAX UNIT
Supply voltage, VCC 3 3.3 3.6 V
LVDS output supply voltage, LVDSVCC 3 3.3 3.6
PLL analog supply voltage, PLLVCC 3 3.3 3.6
IO input reference supply voltage, IOVCC 1.62 1.8 / 2.5 / 3.3 3.6
Power supply noise on any VCC terminal 0.1
High-level input voltage, VIH IOVCC = 1.8 V IOVCC/2 + 0.3 V V
IOVCC = 2.5 V IOVCC/2 + 0.4 V
IOVCC = 3.3 V IOVCC/2 + 0.5 V
Low-level input voltage, VIL IOVCC = 1.8 V IOVCC/2 – 0.3 V V
IOVCC = 2.5 V IOVCC/2 – 0.4 V
IOVCC = 3.3 V IOVCC/2 – 0.5 V
Differential load impedance, ZL 90 132 Ω
Operating free-air temperature, TA –45 85 °C

7.4 Thermal Information

THERMAL METRIC(1) SN65LVDS93A UNIT
ZQL (BGA MICROSTAR) DGG (TSSOP)
56 PINS 56 PINS
RθJA Junction-to-ambient thermal resistance 67.1 62.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 25.2 18.4
RθJB Junction-to-board thermal resistance 31.0 31.1
ψJT Junction-to-top characterization parameter 0.8 0.8
ψJB Junction-to-board characterization parameter 30.3 30.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VT Input voltage threshold RL = 100 Ω, See Figure 7 IOVCC/2 V
|VOD| Differential steady-state output voltage magnitude 250 450 mV
Δ|VOD| Change in the steady-state differential output voltage magnitude between opposite binary states 1 35 mV
VOC(SS) Steady-state common-mode output voltage See Figure 7
tR/F (Dx, CLKin) = 1 ns		 1.125 1.375 V
VOC(PP) Peak-to-peak common-mode output voltage 35 mV
IIH High-level input current VIH = IOVCC 25 μA
IIL Low-level input current VIL = 0 V ±10 μA
IOS Short-circuit output current VOY = 0 V ±24 mA
VOD = 0 V ±12 mA
IOZ High-impedance state output current VO = 0 V to VCC ±20 μA
Rpdn Input pulldown integrated resistor on all inputs (Dx, CLKSEL, SHTDN, CLKIN) IOVCC = 1.8 V 200 kΩ
IOVCC = 3.3 V 100
IQ Quiescent current Disabled, all inputs at GND;
SHTDN = VIL		 2 100 μA
ICC Supply current (average) SHTDN = VIH, RL = 100 Ω (5 places), grayscale pattern (Figure 8)
VCC = 3.3 V, fCLK = 75 MHz
I(VCC) + I(PLLVCC) + I(LVDSVCC) 51.9 mA
I(IOVCC) with IOVCC = 3.3 V 0.4
I(IOVCC) with IOVCC = 1.8 V 0.1
SHTDN = VIH, RL = 100 Ω (5 places), 50% transition density pattern (Figure 8),
VCC = 3. 3 V, fCLK = 75 MHz
I(VCC) + I(PLLVCC) + I(LVDSVCC) 53.3 mA
I(IOVCC) with IOVCC = 3.3 V 0.6
I(IOVCC) with IOVCC = 1.8 V 0.2
SHTDN = VIH, RL = 100 Ω (5 places), worst-case pattern (Figure 9),
VCC = 3.6 V, fCLK = 75 MHz
I(VCC) + I(PLLVCC) + I(LVDSVCC) 63.7 mA
I(IOVCC) with IOVCC = 3.3 V 1.3
I(IOVCC) with IOVCC = 1.8 V 0.5
SHTDN = VIH, RL = 100 Ω (5 places), worst-case pattern (Figure 9),
fCLK = 100 MHz
I(VCC) + I(PLLVCC) + I(LVDSVCC) 81.6 mA
I(IOVCC) with IOVCC = 3.6 V 1.6
I(IOVCC) with IOVCC = 1.8 V 0.6
SHTDN = VIH, RL = 100 Ω (5 places), worst-case pattern (Figure 9),
fCLK = 135 MHz
I(VCC) + I(PLLVCC) + I(LVDSVCC) 102.2 mA
I(IOVCC) with IOVCC = 3.6 V 2.1
I(IOVCC) with IOVCC = 1.8 V 0.8
CI Input capacitance 2 pF
(1) All typical values are at VCC = 3.3 V, TA = 25°C.

7.6 Timing Requirements

MIN MAX UNIT
Input clock period, tc 7.4 100 ns
Input clock modulation w/ modulation frequency 30 kHz 8%
w/ modulation frequency 50 kHz 6%
High-level input clock pulse width duration, tw 0.4 tc 0.6 tc ns
Input signal transition time, tt 3 ns
Data set up time, D0 through D27 before CLKIN (See Figure 6) 2 ns
Data hold time, D0 through D27 after CLKIN 0.8 ns

7.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS MIN TYP(1) MAX UNIT
t0 Delay time, CLKOUT↑ after Yn valid (serial bit position 0, equal D1, D9, D20, D5) See Figure 10, tC = 10 ns,
|Input clock jitter| < 25 ps (2)		 –0.1 0 0.1 ns
t1 Delay time, CLKOUT↑ after Yn valid (serial bit position 1, equal D0, D8, D19, D27) 1/7 tc – 0.1 1/7 tc + 0.1 ns
t2 Delay time, CLKOUT↑ after Yn valid (serial bit position 2, equal D7, D18, D26. D23) 2/7 tc – 0.1 2/7 tc + 0.1 ns
t3 Delay time, CLKOUT↑ after Yn valid (serial bit position 3; equal D6, D15, D25, D17) 3/7 tc – 0.1 3/7 tc + 0.1 ns
t4 Delay time, CLKOUT↑ after Yn valid (serial bit position 4, equal D4, D14, D24, D16) 4/7 tc – 0.1 4/7 tc + 0.1 ns
t5 Delay time, CLKOUT↑ after Yn valid (serial bit position 5, equal D3, D13, D22, D11) 5/7 tc – 0.1 5/7 tc + 0.1 ns
t6 Delay time, CLKOUT↑ after Yn valid (serial bit position 6, equal D2, D12, D21, D10) 6/7 tc – 0.1 6/7 tc + 0.1 ns
tc(o) Output clock period tc ns
Δtc(o) Output clock cycle-to-cycle jitter (3) tC = 10 ns; clean reference clock, see Figure 11 ±26 ps
tC = 10 ns with 0.05UI added noise modulated at 3 MHz, see Figure 11 ±44
tC = 7.4 ns; clean reference clock, see Figure 11 ±35
tC = 7.4 ns with 0.05UI added noise modulated at 3 MHz, see Figure 11 ±42
tw High-level output clock pulse duration 4/7 tc ns
tr/f Differential output voltage transition time (tr or tf) See Figure 7 225 500 ps
ten Enable time, SHTDN↑ to phase lock (Yn valid) f(clk) = 135 MHz, See Figure 12 6 µs
tdis Disable time, SHTDN↓ to off-state (CLKOUT high-impedance) f(clk) = 135 MHz, See Figure 13 7 ns
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) |Input clock jitter| is the magnitude of the change in the input clock period.
(3) The output clock cycle-to-cycle jitter is the largest recorded change in the output clock period from one cycle to the next cycle observed over 15,000 cycles.Tektronix TDSJIT3 Jitter Analysis software was used to derive the maximum and minimum jitter value.
SN65LVDS93A load_seq_lls846.gifFigure 1. Typical SN65LVDS93A Load and Shift Sequences

7.8 Typical Characteristics

SN65LVDS93A gscale_v_clk_llsem1.gif
Total device current (using grayscale pattern) over pixel clock frequency
Figure 2. Average Grayscale ICC vs Clock Frequency
SN65LVDS93A typ_prbs_llsem1.gif
Clock signal = 135 MHz
Figure 4. Typical PRBS Output Signal
Over One Clock Period
SN65LVDS93A outjit_v_freq_llsem1.gif
CLK frequency during text = 100 MHz
Figure 3. Output Clock Jitter vs Input Clock Jitter