SLLSF42A
March 2018 – May 2018
SN65LVDS93B-Q1
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Simplified Schematic
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Switching Characteristics
6.8
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
TTL Input Data
8.3.2
LVDS Output Data
8.4
Device Functional Modes
8.4.1
Input Clock Edge
8.4.2
Low Power Mode
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Power Up Sequence
9.2.2.2
Signal Connectivity
9.2.2.3
PCB Routing
9.2.3
Application Curve
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.1.1
Board Stackup
11.1.2
Power and Ground Planes
11.1.3
Traces, Vias, and Other PCB Components
11.2
Layout Example
12
Device and Documentation Support
12.1
Trademarks
12.2
Electrostatic Discharge Caution
12.3
Receiving Notification of Documentation Updates
12.4
Community Resources
12.5
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DGG|56
MPDS570
Thermal pad, mechanical data (Package|Pins)
Orderable Information
sllsf42a_oa
sllsf42a_pm
11.1
Layout Guidelines