SLLSF42A March 2018 – May 2018 SN65LVDS93B-Q1
PRODUCTION DATA.
The SN65LVDS93B-Q1 can be put in low-power consumption mode by active-low input SHTDN#. Connecting pin SHTDN# to GND will inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers to a low-level. Populate a pull-up to VCC on SHTDN# to enable the device for normal operation.