SLLSF42A March   2018  – May 2018 SN65LVDS93B-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 TTL Input Data
      2. 8.3.2 LVDS Output Data
    4. 8.4 Device Functional Modes
      1. 8.4.1 Input Clock Edge
      2. 8.4.2 Low Power Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Power Up Sequence
        2. 9.2.2.2 Signal Connectivity
        3. 9.2.2.3 PCB Routing
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Stackup
      2. 11.1.2 Power and Ground Planes
      3. 11.1.3 Traces, Vias, and Other PCB Components
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.2 Signal Connectivity

While there is no formal industry standardized specification for the input interface of LVDS LCD panels, the industry has aligned over the years on a certain data format (bit order). Figure 13 through Figure 15 show how each signal should be connected from the graphic source through the SN65LVDS93B-Q1 input, output and LVDS LCD panel input. Detailed notes are provided with each figure.

SN65LVDS93B-Q1 lcd_24bit_llsem2.gif
Note A. FORMAT: The majority of 24-bit LCD display panels require the two most significant bits (2 MSB ) of each color to be transferred over the 4th serial data output Y3. A few 24-bit LCD display panels require the two LSBs of each color to be transmitted over the Y3 output. The system designer needs to verify which format is expected by checking the LCD display data sheet.
  • Format 1: use with displays expecting the 2 MSB to be transmitted over the 4th data channel Y3. This is the dominate data format for LCD panels.
  • Format 2: use with displays expecting the 2 LSB to be transmitted over the 4th data channel.
Note B. Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
  • C1: decoupling cap for the VDDIO supply; install at least 1x0.01µF.
  • C2: decoupling cap for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
  • C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.
Note C. If RSVD is not driven to a valid logic level, then an external connection to GND is recommended.
Note D. RSVD must be driven to a valid logic level. All unused SN65LVDS93B-Q1 inputs must be tied to a valid logic level.
Figure 13. 24-Bit Color Host to 24-Bit LCD Panel Application
SN65LVDS93B-Q1 lcd_18bit_llsem2.gif
Note A. Leave output Y3 NC.
Note B.Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
  • C1: decoupling cap for the VDDIO supply; install at least 1x0.01µF.
  • C2: decoupling cap for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
  • C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.
Figure 14. 18-Bit Color Host to 18-Bit Color LCD Panel Display Application
SN65LVDS93B-Q1 lcd_24to18bit_llsem2.gif
Note A. Leave output Y3 NC.
Note B. R0, R1, G0, G1, B0, B1: For improved image quality, the GPU should dither the 24-bit output pixel down to18-bit per pixel.
NoteC.Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
  • C1: decoupling cap for the VDDIO supply; install at least 1x0.01µF.
  • C2: decoupling cap for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
  • C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.
Figure 15. 24-Bit Color Host to 18-Bit Color LCD Panel Display Application