SLLS373M July   1999  – March 2024 SN65LVDS1 , SN65LVDS2 , SN65LVDT2

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Driver Electrical Characteristics
    6. 6.6 Receiver Electrical Characteristics
    7. 6.7 Driver Switching Characteristics
    8. 6.8 Receiver Switching Characteristics
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 SN65LVDS1 Features
        1. 8.3.1.1 Driver Output Voltage and Power-On Reset
        2. 8.3.1.2 Driver Offset
        3. 8.3.1.3 5-V Input Tolerance
        4. 8.3.1.4 NC Pins
        5. 8.3.1.5 Driver Equivalent Schematics
      2. 8.3.2 SN65LVDS2 and SN65LVDT2 Features
        1. 8.3.2.1 Receiver Open Circuit Fail-Safe
        2. 8.3.2.2 Receiver Output Voltage and Power-On Reset
        3. 8.3.2.3 Common-Mode Range vs Supply Voltage
        4. 8.3.2.4 General Purpose Comparator
        5. 8.3.2.5 Receiver Equivalent Schematics
        6. 8.3.2.6 NC Pins
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation With VCC < 1.5 V
      2. 8.4.2 Operation With 1.5 V ≤ VCC < 2.4 V
      3. 8.4.3 Operation With 2.4 V ≤ VCC < 3.6 V
      4. 8.4.4 SN65LVDS1 Truth Table
      5. 8.4.5 SN65LVDS2 and SN65LVDT2 Truth Table
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Point-to-Point Communications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Driver Supply Voltage
          2. 9.2.1.2.2  Driver Bypass Capacitance
          3. 9.2.1.2.3  Driver Input Voltage
          4. 9.2.1.2.4  Driver Output Voltage
          5. 9.2.1.2.5  Interconnecting Media
          6. 9.2.1.2.6  PCB Transmission Lines
          7. 9.2.1.2.7  Termination Resistor
          8. 9.2.1.2.8  Driver NC Pins
          9. 9.2.1.2.9  Receiver Supply Voltage
          10. 9.2.1.2.10 Receiver Bypass Capacitance
          11. 9.2.1.2.11 Receiver Input Common-Mode Range
          12. 9.2.1.2.12 Receiver Input Signal
          13. 9.2.1.2.13 Receiver Output Signal
          14. 9.2.1.2.14 Receiver NC Pins
      2. 9.2.2 Application Curve
      3. 9.2.3 Multidrop Communications
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1 Interconnecting Media
        3. 9.2.3.3 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Microstrip vs. Stripline Topologies
      2. 11.1.2 Dielectric Type and Board Construction
      3. 11.1.3 Recommended Stack Layout
      4. 11.1.4 Separation Between Traces
      5. 11.1.5 Crosstalk and Ground Bounce Minimization
      6. 11.1.6 Decoupling
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Other LVDS Products
    2. 12.2 Third-Party Products Disclaimer
    3. 12.3 Documentation Support
      1. 12.3.1 Related Information
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Support Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DBV|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11.1.4 Separation Between Traces

The separation between traces depends on several factors; however, the amount of coupling that can be tolerated usually dictates the actual separation. Low noise coupling requires close coupling between the differential pair of an LVDS link to benefit from the electromagnetic field cancellation. The traces should be 100-Ω differential and thus coupled in the manner that best fits this requirement. In addition, differential pairs should have the same electrical length to ensure that they are balanced, thus minimizing problems with skew and signal reflection.

In the case of two adjacent single-ended traces, one should use the 3-W rule, which stipulates that the distance between two traces must be greater than two times the width of a single trace, or three times its width measured from trace center to trace center. This increased separation effectively reduces the potential for crosstalk. The same rule should be applied to the separation between adjacent LVDS differential pairs, whether the traces are edge-coupled or broad-side-coupled.

SN65LVDS1 SN65LVDS2 SN65LVDT2 3-W Rule for Single-Ended and Differential Traces (Top View) Figure 11-5 3-W Rule for Single-Ended and Differential Traces (Top View)

You should exercise caution when using autorouters, because they do not always account for all factors affecting crosstalk and signal reflection. For instance, it is best to avoid sharp 90° turns to prevent discontinuities in the signal path. Using successive 45° turns tends to minimize reflections.