SLLS902A February   2010  – March 2024 SN65MLVD040

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Reccommended Operationg Conditions
    3. 5.3  Thermal Characteristics
    4. 5.4  Package Dissipation Ratings
    5. 5.5  Device Electrical Characteristics
    6. 5.6  Driver Electrical Characteristics
    7. 5.7  Reciver Electrical Charecteristics
    8. 5.8  Bus Input and Output Electrical Characteristics
    9. 5.9  Driver Switching Characterisitics
    10. 5.10 Reciever Switching Charecteristics
    11. 5.11 Typical Characteristics
  7. 6 Paramater Measurement Information
    1. 6.1 Equivalent Input and Output Schematic Diagrams
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Source Synchronous System Clock (SSSC)
        1. 7.1.1.1 Live Insertion/Glitch-Free Power Up/Down
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.9 Driver Switching Characterisitics

over recommended operating conditions unless otherwise noted
PARAMETERTEST CONDITIONSMINTYP(1)MAXUNIT
tpLHPropagation delay time, low-to-high-level outputSee Figure 6-51.31.92.4ns
tpHLPropagation delay time, high-to-low-level output1.31.92.4ns
trDifferential output signal rise time0.92ns
tfDifferential output signal fall time0.92.2ns
tsk(o)Output skew200ps
tsk(p)Pulse skew (|tPHL – tPLH|)150ps
tsk(pp)Part-to-part skew (2)300ps
tjit(per)Period jitter, rms (1 standard deviation)(3)All channels switching, 125 MHz clock input(4), see Figure 6-82ps
tjit(c-c)Cycle-to-cycle jitter, rms(3)9ps
tjit(det)Deterministic jitter(3)All channels switching, 250 Mbps 215–1 PRBS input(4), see Figure 6-8290ps
tjit(r)Random jitter(3)4ps
tPZHEnable time, high-impedance-to-high-level outputSee Figure 6-67ns
tPZLEnable time, high-impedance-to-low-level output7ns
tPHZDisable time, high-level-to-high-impedance output7ns
tPLZDisable time, low-level-to-high-impedance output7ns
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
(2) tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
(4) tr = tf = 0.5 ns (10% to 90%)