SLLS902A February   2010  – March 2024 SN65MLVD040

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Reccommended Operationg Conditions
    3. 5.3  Thermal Characteristics
    4. 5.4  Package Dissipation Ratings
    5. 5.5  Device Electrical Characteristics
    6. 5.6  Driver Electrical Characteristics
    7. 5.7  Reciver Electrical Charecteristics
    8. 5.8  Bus Input and Output Electrical Characteristics
    9. 5.9  Driver Switching Characterisitics
    10. 5.10 Reciever Switching Charecteristics
    11. 5.11 Typical Characteristics
  7. Paramater Measurement Information
    1. 6.1 Equivalent Input and Output Schematic Diagrams
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Source Synchronous System Clock (SSSC)
        1. 7.1.1.1 Live Insertion/Glitch-Free Power Up/Down
  9. Device and Documentation Support
    1. 8.1 Documentation Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Typical Characteristics

SN65MLVD040 Supply Current vs
                        FrequencyFigure 5-1 Supply Current vs Frequency
SN65MLVD040 Differntial Output Voltage
                        vs FrequencyFigure 5-3 Differntial Output Voltage vs Frequency
SN65MLVD040 Differential Output
                        Voltage vs Trace LengthFigure 5-5 Differential Output Voltage vs Trace Length
SN65MLVD040 Receiver Type-1
                        Propagation Delay vs Free-air TemperatureFigure 5-7 Receiver Type-1 Propagation Delay vs Free-air Temperature
SN65MLVD040 Driver Transition Time vs
                        Free-air TemperatureFigure 5-9 Driver Transition Time vs Free-air Temperature
SN65MLVD040 Type-2 Reciver Transition
                        Time vs Free-Air TemperatureFigure 5-11 Type-2 Reciver Transition Time vs Free-Air Temperature
SN65MLVD040 Added Reciver Type-2
                        Periods Jitter vs FrequencyFigure 5-13 Added Reciver Type-2 Periods Jitter vs Frequency
SN65MLVD040 Added Reciver Type-1
                        Cycle-to-Cycle Jitter vs FrequencyFigure 5-15 Added Reciver Type-1 Cycle-to-Cycle Jitter vs Frequency
SN65MLVD040 Added Driver
                        Cycle-to-Cylce Jitter vs FrequencyFigure 5-17 Added Driver Cycle-to-Cylce Jitter vs Frequency
SN65MLVD040 Added Reciver Type-1
                        Deterministic Jitter vs Data RateFigure 5-19 Added Reciver Type-1 Deterministic Jitter vs Data Rate
SN65MLVD040 Reciver Output Eye Pattern
                        250 Mbps, 215–1 PRBS, VCC = 3.3 V|VID| =
                        400 mVPP, VIC = 1 VFigure 5-21 Reciver Output Eye Pattern 250 Mbps, 215–1 PRBS, VCC = 3.3 V|VID| = 400 mVPP, VIC = 1 V
SN65MLVD040 Supply Current vs Free-air
                        TemperatureFigure 5-2 Supply Current vs Free-air Temperature
SN65MLVD040 Differential Output
                        Voltage vs FrequencyFigure 5-4 Differential Output Voltage vs Frequency
SN65MLVD040 Driver Propagation Delay
                        vs Free-Air TemperatureFigure 5-6 Driver Propagation Delay vs Free-Air Temperature
SN65MLVD040 Receiver Type-2
                        Propagation Delay vs Free-air TemperatureFigure 5-8 Receiver Type-2 Propagation Delay vs Free-air Temperature
SN65MLVD040 Type-1 Reciver Transition
                        Time vs Free-Air TemperatureFigure 5-10 Type-1 Reciver Transition Time vs Free-Air Temperature
SN65MLVD040 Added Reciver Type-1
                        Period Jitter vs FrequencyFigure 5-12 Added Reciver Type-1 Period Jitter vs Frequency
SN65MLVD040 Added Period Driver Jitter
                        vs FrequencyFigure 5-14 Added Period Driver Jitter vs Frequency
SN65MLVD040 Added Reciver Type-2
                        Cycle-to-Cycle Jitter vs FrequencyFigure 5-16 Added Reciver Type-2 Cycle-to-Cycle Jitter vs Frequency
SN65MLVD040 Added Reciver Type-1
                        Deterministic Jitter vs Data RateFigure 5-18 Added Reciver Type-1 Deterministic Jitter vs Data Rate
SN65MLVD040 Driver Output Eye Pattern
                        250 Mbps, 215–1 PRBS, VCC = 3.3 VFigure 5-20 Driver Output Eye Pattern 250 Mbps, 215–1 PRBS, VCC = 3.3 V
SN65MLVD040 Reciver Output Eye Pattern
                        250 Mbps, 215–1 PRBS, VCC = 3.3 V|VID| =
                        800 mVPP, VIC = 1 VFigure 5-22 Reciver Output Eye Pattern 250 Mbps, 215–1 PRBS, VCC = 3.3 V|VID| = 800 mVPP, VIC = 1 V