SLLS902A February   2010  – March 2024 SN65MLVD040

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Reccommended Operationg Conditions
    3. 5.3  Thermal Characteristics
    4. 5.4  Package Dissipation Ratings
    5. 5.5  Device Electrical Characteristics
    6. 5.6  Driver Electrical Characteristics
    7. 5.7  Reciver Electrical Charecteristics
    8. 5.8  Bus Input and Output Electrical Characteristics
    9. 5.9  Driver Switching Characterisitics
    10. 5.10 Reciever Switching Charecteristics
    11. 5.11 Typical Characteristics
  7. 6 Paramater Measurement Information
    1. 6.1 Equivalent Input and Output Schematic Diagrams
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Source Synchronous System Clock (SSSC)
        1. 7.1.1.1 Live Insertion/Glitch-Free Power Up/Down
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Driver Electrical Characteristics

over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX UNIT
|VAB| Differential output voltage magnitude (A, B) See Figure 6-2 480 650 mV
Δ|VAB| Change in differential output voltage magnitude
between logic states (A, B)		 –50 50 mV
VOS(SS) Steady-state common-mode output voltage (A, B) See Figure 6-3 0.7 1.1 V
ΔVOS(SS) Change in steady-state common-mode output voltage between logic states (A, B) –50 50 mV
VOS(PP) Peak-to-peak common-mode output voltage (A, B) 150 mV
VA(OC) Maximum steady-state open-circuit output voltage (A, B) See Figure 6-7 0 2.4 V
VB(OC) Maximum steady-state open-circuit output voltage (A, B) 0 2.4 V
VP(H) Voltage overshoot, low-to-high level output (A, B) See Figure 6-5 1.2 VSS V
VP(L) Voltage overshoot, high-to-low level output (A, B) –0.2 VSS V
IIH High-level input current (D, DE) VIH = 2 V to VCC 10 μA
IIL Low-level input current (D, DE) VIL = GND to 0.8 V 10 μA
|IOS| Differential short-circuit output current magnitude (A, B) See Figure 6-4 24 mA
CI Input capacitance (D, DE) VI = 0.4 sin(30E6πt) + 0.5 V (3) 5 pF
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(2) All typical values are at 25°C and with a 3.3-V supply voltage.
(3) HP4194A impedance analyzer (or equivalent)