SLLS736B July   2006  – March 2024 SN65MLVD047A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Package Dissipation Ratings
    5. 5.5 Thermal Information
    6. 5.6 Device Electrical Characteristics
    7. 5.7 Device Electrical Characteristics
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Synchroization Clock in AdvancedTCA
      2. 8.1.2 Multipoint Configuration
      3. 8.1.3 Multidrop Configuration
      4. 8.1.4 Unused Channel
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Parameter Measurement Information

GUID-C6AD95E3-6028-42D2-B751-7EAEF24D0AC5-low.gifFigure 6-1 Driver Voltage and Current Definitions
GUID-E415695D-DBD0-4E56-9DEF-95942FDC5490-low.gif
All resistors are 1% tolerance.
Figure 6-2 Differential Output Voltage Test Circuit
GUID-82AA2EC7-A1B5-4BA4-B977-4EFCAFAB7801-low.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1ns, pulse frequency = 500kHz, duty cycle = 50 ± 5%.
B. C1, C2 and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 and R2 are metal film, surface mount, ±1%, and located within 2 cm of the D.U.T.
D. The measurement of VOS(PP) is made on test equipment with a –3dB bandwidth of at least 1 GHz.
Figure 6-3 Test Circuit and Definitions for the Common-Mode Output Voltage
GUID-9736E077-D2B0-4708-BD49-540788AFF4B4-low.gifFigure 6-4 Short-Circuit Test Circuit
GUID-ADC765DA-5BDD-49CF-B5BA-819512B7D9D6-low.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1ns, frequency = 500kHz, duty cycle = 50 ± 5%.
B. C1, C2, and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 is a metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a –3dB bandwidth of at least 1 GHz.
Figure 6-5 Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
GUID-4306FC80-3D98-4F74-9FE4-CFF52077B0B8-low.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1ns, frequency = 500kHz, duty cycle = 50 ± 5%.
B. C1, C2, C3, and C4 includes instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 and R2 are metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a –3dB bandwidth of at least 1GHz.
Figure 6-6 Driver Enable and Disable Time Circuit and Definitions
GUID-46121D72-4D66-434B-9E13-B4EC4B627FCD-low.gifFigure 6-7 Driver Maximum Steady State Output Voltage
GUID-81458588-9803-4A7A-819F-31028C6FCF13-low.gif
A. All input pulses are supplied by an Agilent 8304A Stimulus System.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter and cycle-to-cycle jitter are measured using a 100MHz 50 ±1% duty cycle clock input.
D. Peak-to-peak jitter is measured using a 200Mbps 215 – 1PRBS input.
Figure 6-8 Driver Jitter Measurement Waveforms