SLLS573E December   2003  – March 2024 SN65MLVD200A , SN65MLVD202A , SN65MLVD204A , SN65MLVD205A

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics – Driver
    7. 6.7  Electrical Characteristics – Receiver
    8. 6.8  Electrical Characteristics – BUS Input and Output
    9. 6.9  Switching Characteristics – Driver
    10. 6.10 Switching Characteristics – Receiver
    11. 6.11 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power-On Reset
      2. 8.3.2 ESD Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Function Tables
      2. 8.4.2 Equivalent Input and Output Schematic Diagrams
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Supply Voltage
        2. 9.2.2.2  Supply Bypass Capacitance
        3. 9.2.2.3  Driver Input Voltage
        4. 9.2.2.4  Driver Output Voltage
        5. 9.2.2.5  Termination Resistors
        6. 9.2.2.6  Receiver Input Signal
        7. 9.2.2.7  Receiver Input Threshold (Failsafe)
        8. 9.2.2.8  Receiver Output Signal
        9. 9.2.2.9  Interconnecting Media
        10. 9.2.2.10 PCB Transmission Lines
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Microstrip Versus Stripline Topologies
      2. 11.1.2 Dielectric Type and Board Construction
      3. 11.1.3 Recommended Stack Layout
      4. 11.1.4 Separation Between Traces
      5. 11.1.5 Crosstalk and Ground Bounce Minimization
      6. 11.1.6 Decoupling
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Example

At least two or three times the width of an individual trace must separate single-ended traces and differential pairs to minimize the potential for crosstalk. Single-ended traces that run in parallel for less than the wavelength of the rise or fall times usually have negligible crosstalk. Increase the spacing between signal paths for long parallel runs to reduce crosstalk. Boards with limited real estate can benefit from the staggered trace layout, as shown in Figure 11-9.

SN65MLVD200A SN65MLVD202A  SN65MLVD204A SN65MLVD205A Staggered Trace LayoutFigure 11-9 Staggered Trace Layout

This configuration lays out alternating signal traces on different layers; thus, the horizontal separation between traces can be less than 2 or 3 times the width of individual traces. To ensure continuity in the ground signal path, TI recommends having an adjacent ground via for every signal via, as shown in Figure 11-10.

Note:

Vias create additional capacitance. For example, a typical via has a lumped capacitance effect of ½ pF to 1 pF in FR4.

SN65MLVD200A SN65MLVD202A  SN65MLVD204A SN65MLVD205A Ground Via Location (Side View)Figure 11-10 Ground Via Location (Side View)

Short and low-impedance connection of the device ground pins to the PCB ground plane reduces ground bounce. Holes and cutouts in the ground planes can adversely affect current return paths if they create discontinuities that increase returning current loop areas.

To minimize EMI problems, TI recommends avoiding discontinuities below a trace (for example, holes, slits, and so on) and keeping traces as short as possible. Zoning the board wisely by placing all similar functions in the same area, as opposed to mixing them together, helps reduce susceptibility issues.