SLLS573E December 2003 – March 2024 SN65MLVD200A , SN65MLVD202A , SN65MLVD204A , SN65MLVD205A
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VIT+ | Positive-going differential input voltage threshold | Type 1 | See Figure 6-9, Table 7-1, and Table 7-2 | 50 | mV | ||
Type 2 | 150 | ||||||
VIT- | Negative-going differential input voltage threshold | Type 1 | –50 | mV | |||
Type 2 | 50 | ||||||
VHYS | Differential input voltage hysteresis, (VIT+ – VIT–) | Type 1 | 25 | mV | |||
Type 2 | 0 | ||||||
VOH | High-level output voltage (R) | IOH = –8 mA | 2.4 | V | |||
VOL | Low-level output voltage (R) | IOL = 8 mA | 0.4 | V | |||
IIH | High-level input current ( RE) | VIH = 2 V to VCC | –10 | 0 | µA | ||
IIL | Low-level input current ( RE) | VIL = GND to 0.8 V | –10 | 0 | µA | ||
IOZ | High-impedance output current (R) | VO = 0 V or 3.6 V | –10 | 15 | µA | ||
CA or CB | Input capacitance | VI = 0.4 sin(30E6πt) + 0.5 V(2), Other input at 1.2 V |
3 | pF | |||
CAB | Differential input capacitance | VAB = 0.4 sin(30E6πt) V(2) | 2.5 | pF | |||
CA/B | Input capacitance balance, (CA/CB) | 0.99 | 1.01 |