Each power or ground lead of a high-speed device must be connected to the PCB through a low inductance path. For best results, one or more vias are used to connect a power or ground pin to the nearby plane. Ideally, via placement is immediately adjacent to the pin to avoid adding trace inductance. Placing a power plane closer to the top of the board reduces the effective via length and its associated inductance.

Figure 11-6 Low Inductance, High-Capacitance Power Connection

Bypass capacitors must be placed close to V_DD pins and can be placed conveniently near the corners or underneath the package to minimize the loop area. This extends the useful frequency range of the added capacitance. Small physical-size capacitors (such as 0402, 0201, or X7R surface-mount capacitors) must be used to minimize body inductance of capacitors. Each bypass capacitor is connected to the power and ground plane through vias tangent to the pads of the capacitor as shown in Figure 11-7(a).

An X7R surface-mount capacitor of size 0402 has about 0.5 nH of body inductance. At frequencies above about 30 MHz, X7R capacitors behave as low-impedance inductors. To extend the operating frequency range to a few hundred MHz, an array of different capacitor values like 100 pF, 1 nF, 0.03 μF, and 0.1 μF are commonly used in parallel. The most effective bypass capacitor can be built using sandwiched layers of power and ground at a separation of 2 to 3 mils. With a 2-mil FR4 dielectric, there is approximately 500 pF per square inch of PCB.

Many high-speed devices provide a low-inductance GND connection on the backside of the package. This center pad must be connected to a ground plane through an array of vias. The via array reduces the effective inductance to ground and enhances the thermal performance of the small surface mount technology (SMT) package. Placing vias around the perimeter of the pad connection ensures proper heat spreading and the lowest possible die temperature. Placing high-performance devices on opposing sides of the PCB using two GND planes (as shown in Figure 9-4) creates multiple paths for heat transfer.

Thermal PCB issues are often the result of one device adding heat to another, resulting in a very high local temperature. Multiple paths for heat transfer minimize this possibility. In many cases, the GND pad that is so important for heat dissipation makes the optimal decoupling layout impossible to achieve, due to insufficient pad-to-pad spacing as shown in Figure 11-8(b). When this occurs, placing the decoupling capacitor on the backside of the board keeps the extra inductance to a minimum.

It is important to place the V_DD via as close to the device pin as possible while still allowing for sufficient solder mask coverage. If the via is left open, solder may flow from the pad into the via barrel, which results in a poor solder connection

Figure 11-7 Typical Decoupling Capacitor Layout (a)

Figure 11-8 Typical Decoupling Capacitor Layout (b)