SLLSEX9A December   2016  – February 2020 SN65MLVD206B

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic, SN65MLVD206B
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. Table 1.  Absolute Maximum Ratings
    2. Table 2.  ESD Ratings
    3. Table 3.  Recommended Operating Conditions
    4. Table 4.  Thermal Information
    5. Table 5.  Electrical Characteristics
    6. Table 6.  Electrical Characteristics – Driver
    7. Table 7.  Electrical Characteristics – Receiver
    8. Table 8.  Electrical Characteristics – BUS Input and Output
    9. Table 9.  Switching Characteristics – Driver
    10. Table 10. Switching Characteristics – Receiver
    11. 6.1       Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Power-On-Reset
      2. 8.3.2 ESD Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation with VCC < 1.5 V
      2. 8.4.2 Operations with 1.5 V ≤ VCC < 3 V
      3. 8.4.3 Operation with 3 V ≤ VCC < 3.6 V
      4. 8.4.4 Device Function Tables
      5. 8.4.5 Equivalent Input and Output Schematic Diagrams
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Multipoint Communications
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1  Supply Voltage
        2. 9.2.3.2  Supply Bypass Capacitance
        3. 9.2.3.3  Driver Input Voltage
        4. 9.2.3.4  Driver Output Voltage
        5. 9.2.3.5  Termination Resistors
        6. 9.2.3.6  Receiver Input Signal
        7. 9.2.3.7  Receiver Input Threshold (Failsafe)
        8. 9.2.3.8  Receiver Output Signal
        9. 9.2.3.9  Interconnecting Media
        10. 9.2.3.10 PCB Transmission Lines
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Microstrip vs. Stripline Topologies
      2. 11.1.2 Dielectric Type and Board Construction
      3. 11.1.3 Recommended Stack Layout
      4. 11.1.4 Separation Between Traces
      5. 11.1.5 Crosstalk and Ground Bounce Minimization
      6. 11.1.6 Decoupling
        1.       (a)
        2.       (b)
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11.1.2 Dielectric Type and Board Construction

The speeds at which signals travel across the board dictates the choice of dielectric. FR-4, or equivalent, usually provides adequate performance for use with M-LVDS signals. If rise or fall times of TTL/CMOS signals are less than 500 ps, empirical results indicate that a material with a dielectric constant near 3.4, such as Rogers™ 4350 or Nelco N4000-13 is better suited. Once the designer chooses the dielectric, there are several parameters pertaining to the board construction that can affect performance. The following set of guidelines were developed experimentally through several designs involving M-LVDS devices:

  • Copper weight: 15 g or 1/2 oz start, plated to 30 g or 1 oz
  • All exposed circuitry should be solder-plated (60/40) to 7.62 μm or 0.0003 in (minimum).
  • Copper plating should be 25.4 μm or 0.001 in (minimum) in plated-through-holes.
  • Solder mask over bare copper with solder hot-air leveling