SCAS786D November   2004  – July 2024 SN74AC04-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Operating Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 16
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application Information Disclaimer
    1. 8.1 Power Supply Recommendations
    2. 8.2 Layout
      1. 8.2.1 Layout Guidelines
      2. 8.2.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The SN74AC04-Q1 device contains six independent inverters. The device performs the Boolean function Y = A.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3)
SN74AC04-Q1 BQA (WQFN, 14) 3.00mm × 2.50mm 3.00mm × 2.50mm
PW (TSSOP, 14) 5mm × 6.4mm 5mm × 4.4mm
(1) For more information, see Section 11.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
(3) The body size (length × width) is a nominal value and does not include pins.
SN74AC04-Q1 Logic Diagram (Positive Logic)Logic Diagram (Positive Logic)