SCAS959A November   2023  – March 2024 SN74AC573-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7. 5.7 Switching Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Balanced CMOS 3-State Outputs
      2. 6.3.2 Latching Logic
      3. 6.3.3 Standard CMOS Inputs
      4. 6.3.4 Clamp Diode Structure
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
    3. 7.3 Design Requirements
      1. 7.3.1 Power Considerations
      2. 7.3.2 Input Considerations
      3. 7.3.3 Output Considerations
    4. 7.4 Detailed Design Procedure
    5. 7.5 Application Curve
    6. 7.6 Power Supply Recommendations
    7. 7.7 Layout
      1. 7.7.1 Layout Guidelines
      2. 7.7.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RKS|20
  • PW|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Timing Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER DESCRIPTION CONDITION VCC TA = 25°C -40°C to 85°C -40°C to 125°C UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency 1.5 V 15 11 10 MHz
tW Pulse duration LE high 1.5 V 44 44 50 ns
tW Pulse duration CLK high or low 1.5 V 44 44 50 ns
tW Pulse duration CLR low 1.5 V 35 55 63 ns
tSU Setup time Data before LE↓ 1.5 V 2 2 2 ns
tSU Setup time CLR inactive 1.5 V 2 2 2 ns
tSU Setup time Data before CLK↑ 1.5 V 2 2 2 ns
tH Hold time Data after CLK↑ 1.5 V 2 2 2 ns
tH Hold time Data after LE↓ 1.5 V 15 33 38 ns
fclock Clock frequency 1.8 V 55 45 44 MHz
tW Pulse duration LE high 1.8 V 7.2 11.4 ns
tW Pulse duration CLK high or low 1.8 V 8.6 12.6 ns
tW Pulse duration CLR low 1.8 V 6.5 10.9 ns
tSU Setup time Data before LE↓ 1.8 V 5.1 5.6 ns
tSU Setup time CLR inactive 1.8 V 5.3 5.4 ns
tSU Setup time Data before CLK↑ 1.8 V 8.3 9.5 ns
tH Hold time Data after CLK↑ 1.8 V 2 2 ns
tH Hold time Data after LE↓ 1.8 V 2 2 ns
fclock Clock frequency 2.5 V 90 78 65 MHz
tW Pulse duration LE high 2.5 V 6 6 ns
tW Pulse duration CLK high or low 2.5 V 7.3 7.3 ns
tW Pulse duration CLR low 2.5 V 6 6 ns
tSU Setup time Data before LE↓ 2.5 V 2.4 2.8 ns
tSU Setup time CLR inactive 2.5 V 2.5 2.8 ns
tSU Setup time Data before CLK↑ 2.5 V 3.9 7.5 ns
tH Hold time Data after CLK↑ 2.5 V 1 1 ns
tH Hold time Data after LE↓ 2.5 V 2 2.3 ns
fclock Clock frequency 3.3 V 101 89 75 MHz
tW Pulse duration LE high 3.3 V 5.5 4.9 5.6 ns
tW Pulse duration CLK high or low 3.3 V 5 4.9 5.6 ns
tW Pulse duration CLR low 3.3 V 6.1 7 ns
tSU Setup time Data before LE↓ 3.3 V 3.5 2 2 ns
tSU Setup time CLR inactive 3.3 V 2 2 ns
tSU Setup time Data before CLK↑ 3.3 V 2.5 2 2 ns
tH Hold time Data after CLK↑ 3.3 V 1 1 1 ns
tH Hold time Data after LE↓ 3.3 V 2 2 4.2 ns
fclock Clock frequency 5 V 150 143 125 MHz
tW Pulse duration LE high 5 V 4 3.5 4 ns
tW Pulse duration CLK high or low 5 V 3.5 3.5 4 ns
tW Pulse duration CLR low 5 V 4.4 5 ns
tSU Setup time Data before LE↓ 5 V 3 2 2 ns
tSU Setup time CLR inactive 5 V 2 2 ns
tSU Setup time Data before CLK↑ 5 V 1.5 2 2 ns
tH Hold time Data after CLK↑ 5 V 1 1.5 2 ns
tH Hold time Data after LE↓ 5 V 1 1 1 ns