SCAS959A November   2023  – March 2024 SN74AC573-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7. 5.7 Switching Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Balanced CMOS 3-State Outputs
      2. 6.3.2 Latching Logic
      3. 6.3.3 Standard CMOS Inputs
      4. 6.3.4 Clamp Diode Structure
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
    3. 7.3 Design Requirements
      1. 7.3.1 Power Considerations
      2. 7.3.2 Input Considerations
      3. 7.3.3 Output Considerations
    4. 7.4 Detailed Design Procedure
    5. 7.5 Application Curve
    6. 7.6 Power Supply Recommendations
    7. 7.7 Layout
      1. 7.7.1 Layout Guidelines
      2. 7.7.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RKS|20
  • PW|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The SN74AC573-Q1 contains eight transparent D-type latches with shared 3-state output and latch control.

Package Information
PART NUMBERPACKAGE(1)PACKAGE SIZE(2)BODY SIZE(3)
SN74AC573-Q1 PW (TSSOP, 20) 6.5 mm × 6.4 mm 6.50mm x 4.40mm
RKS (WQFN, 20)4.5 mm × 2.5 mm4.5 mm × 2.5 mm
(1) For more information, see Section 10.
(2) The package size (length × width) is a nominal value and includes pins, where applicable
(3) The body size (length × width) is a nominal value and does not include pins.
GUID-C7F8C849-1ECF-4C8A-B4D9-8230FF0292A9-low.png Logic Diagram (Positive Logic)