SCLSA24 June   2024 SN74AC595

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Switching Characteristics
  7.   15
  8. 6 Parameter Measurement Information
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  10. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 Application Curves
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • BQB|16
  • PW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily for the examples listed in the following table. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1MHz, ZO = 50Ω, tt < 2.5ns.

For clock inputs, fmax is measured when the input duty cycle is 50%.

The outputs are measured individually with one input transition per measurement.

TEST S1 S2 RL CL ΔV VCC
tPLH, tPHL OPEN OPEN — 2.5ns — ALL
tPLZ, tPZL CLOSED OPEN 500Ω 2.5ns 0.15V ≤ 2.5V
tPHZ, tPZH OPEN CLOSED 500Ω 2.5ns 0.15V ≤ 2.5V
tPLZ, tPZL CLOSED OPEN 500Ω 2.5ns 0.3V > 2.5V
tPHZ, tPZH OPEN CLOSED 500Ω 2.5ns 0.3V > 2.5V

SN74AC595 Load Circuit for 3-State Outputs
(1) CL includes probe and test-fixture capacitance.
Figure 6-1 Load Circuit for 3-State Outputs
SN74AC595 Voltage Waveforms, Setup and Hold TimesFigure 6-3 Voltage Waveforms, Setup and Hold Times
SN74AC595 Voltage Waveforms Propagation Delays
(3) The greater between tPZL and tPZH is the same as ten.
(4) The greater between tPLZ and tPHZ is the same as tdis.
Figure 6-5 Voltage Waveforms Propagation Delays
SN74AC595 Voltage Waveforms, Pulse DurationFigure 6-2 Voltage Waveforms, Pulse Duration
SN74AC595 Voltage Waveforms Propagation Delays
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-4 Voltage Waveforms Propagation Delays
SN74AC595 Voltage Waveforms, Input and Output Transition Times
(1) The greater between tr and tf is the same as tt.
Figure 6-6 Voltage Waveforms, Input and Output Transition Times