SCAS962B November   2023  – September 2024 SN74AC8541

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
    4. 6.4 Feature Description
      1. 6.4.1 Balanced CMOS 3-State Outputs
      2. 6.4.2 CMOS Schmitt-Trigger Inputs
      3. 6.4.3 Clamp Diode Structure
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
    3. 7.3 Design Requirements
      1. 7.3.1 Power Considerations
      2. 7.3.2 Input Considerations
      3. 7.3.3 Output Considerations
    4. 7.4 Detailed Design Procedure
    5. 7.5 Application Curves
    6. 7.6 Power Supply Recommendations
    7. 7.7 Layout
      1. 7.7.1 Layout Guidelines
      2. 7.7.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RKS|20
  • DGS|20
  • PW|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted); typical values measured at TA = 25°C
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VT+ Positive-going input threshold voltage 1.5 V 0.61 0.89 1.17 V
1.8 V 0.72 1.03 1.33
2.5 V 0.8 1.29 1.61
3 V 0.8 1.8 2.2
4.5 V 1.5 2.6 3.2
5 V 2.6 2.9 3.4
5.5 V 1.6 3.2 3.9
VT- Negative-going input threshold voltage 1.5 V 0.26 0.48 0.7 V
1.8 V 0.37 0.54 0.70
2.5 V 0.5 0.7 0.84
3 V 0.5 0.8 1.2
4.5 V 0.9 1.4 1.8
5 V 1.6 1.6 2.4
5.5 V 1.1 1.8 2.3
ΔVT Hysteresis (VT+ − VT−) 1.5 V 0.22 0.41 0.6 V
1.8 V 0.28 0.49 0.69
2.5 V 0.3 0.60 0.83
3 V 0.3 1 1.2
4.5 V 0.4 1.2 1.4
5 V 0.5 1.3 1.5
5.5 V 0.5 1.4 1.6
VOH IOH = -50µA 1.5 V 1.4 1.49 V
1.8 V 1.7 1.79
2.5 V 2.4 2.49
3 V 2.9 2.99
4.5 V 4.4 4.49
5.5 V 5.4 5.49
IOH = -1mA 1.8 V 1.44
IOH = -2mA 2.5 V 2
IOH = -4mA 3 V 2.4
IOH = -12mA 3 V 2.4
IOH = -24mA 4.5 V 3.7
IOH = -24mA 5.5 V 4.7
IOH = -75mA 5.5 V
IOH = -50mA 5.5 V 3.85
VOL IOL = 50µA 1.5 V 0.01 0.1 V
1.8 V 0.01 0.1
2.5 V 0.01 0.1
3 V 0.01 0.1
4.5 V 0.01 0.1
5.5 V 0.01 0.1
IOL = 1mA 1.8 V 0.36
IOL = 2mA 2.5 V 0.5
IOL = 4mA 3 V 0.5
IOL = 12mA 3 V 0.5
IOL = 24mA 4.5 V 0.5
IOL = 24mA 5.5 V 0.5
IOL = 50mA 5.5 V 1.65
IOL = 75mA 5.5 V 1.65
II VI = 5.5 V or GND 0 V to 5.5 V ±1 µA
IOZ VO = VCC or GND 5.5 V ±5 µA
ICC VI = VCC or GND, IO = 0 5.5 V 20 µA
CI VI = VCC or GND 5 V 9 pF
CO VO = VCC or GND 5 V 15 pF
CPD(1)(2) F = 1MHz 5 V 60 pF
(1) CPD is used to determine the dynamic power consumption, per channel
(2) PD = VCC2 × FI × (CPD + CL) where FI= input frequency, CL= output load capacitance, VCC= supply voltage