SCASE39
November 2024
SN74ACT3G99
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Switching Characteristics
5.7
Typical Characteristics
6
Parameter Measurement Information
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Combinatorial Logic Configurations
7.4
Feature Description
7.4.1
Balanced CMOS 3-State Outputs
7.4.2
TTL-Compatible Schmitt-Trigger CMOS Inputs
7.4.3
Clamp Diode Structure
7.5
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.1.1
Power Considerations
8.2.1.2
Input Considerations
8.2.1.3
Output Considerations
8.2.2
Detailed Design Procedure
8.2.3
Application Curves
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Documentation Support
9.1.1
Related Documentation
9.2
Receiving Notification of Documentation Updates
9.3
Support Resources
9.4
Trademarks
9.5
Electrostatic Discharge Caution
9.6
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
PW|20
MPDS362A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
scase39_oa
scase39_pm
7.3
Combinatorial Logic Configurations
2-to-1 data selector
2-Input NAND
2-Input AND
2-Input NOR
2-Input OR
Schmitt-trigger buffer
Figure 7-1
Logic Configurations
2-to-1 data selector with inverted output
2-Input NAND with 1 inverted input
2-Input AND with 1 inverted input
2-Input NOR with 1 inverted input
2-Input OR with 1 inverted input
Schmitt-trigger inverter