SCASE39 November   2024 SN74ACT3G99

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Combinatorial Logic Configurations
    4. 7.4 Feature Description
      1. 7.4.1 Balanced CMOS 3-State Outputs
      2. 7.4.2 TTL-Compatible Schmitt-Trigger CMOS Inputs
      3. 7.4.3 Clamp Diode Structure
    5. 7.5 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Combinatorial Logic Configurations

SN74ACT3G99 2-to-1 data
                        selector2-to-1 data selector
SN74ACT3G99 2-Input NAND2-Input NAND
SN74ACT3G99 2-Input AND2-Input AND
SN74ACT3G99 2-Input NOR2-Input NOR
SN74ACT3G99 2-Input OR2-Input OR
SN74ACT3G99 Schmitt-trigger
                        bufferSchmitt-trigger buffer
Figure 7-1 Logic Configurations
SN74ACT3G99 2-to-1 data selector with inverted output2-to-1 data selector with inverted output
SN74ACT3G99 2-Input NAND with 1
                        inverted input2-Input NAND with 1 inverted input
SN74ACT3G99 2-Input AND with 1
                        inverted input2-Input AND with 1 inverted input
SN74ACT3G99 2-Input NOR with 1
                        inverted input2-Input NOR with 1 inverted input
SN74ACT3G99 2-Input OR with 1 inverted
                        input2-Input OR with 1 inverted input
SN74ACT3G99 Schmitt-trigger
                        inverterSchmitt-trigger inverter