SCLS525C July 2003 – April 2024 SN74AHC125-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The SN74AHC125-Q1 is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output.
To put the device in the high-impedance state during power up or power down, tie OE to VCC through a pullup resistor; the current-sinking capability of the driver determines the minimum value of the resistor.
PART NUMBER | PACKAGE1 | PACKAGE SIZE2 |
---|---|---|
SN74AHC125-Q1 | D (SOIC, 14) | 8.65mm × 6mm |
PW (TSSOP, 14) | 5mm × 6.4mm | |
BQA (WQFN, 14) | 3mm × 2.5mm |