SCLS256O December   1995  – February 2024 SN54AHC125 , SN74AHC125

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Switching Characteristics, VCC = 3.3 V ± 0.3 V
    7. 5.7  Switching Characteristics, VCC = 5 V ± 0.5 V
    8. 5.8  Noise Characteristics
    9. 5.9  Operating Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support (Analog)
      1. 9.1.1 Related Documentation
      2. 9.1.2 Related Links
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • RGY|14
  • DB|14
  • DGV|14
  • PW|14
  • BQA|14
  • N|14
  • NS|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The SNx4AHC125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable ( OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output.

To ensure the high-impedance state during power up or power down, OE must be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Device Information
PART NUMBER PACKAGE(1) BODY SIZE(2)
SN54AHC125 J (CDIP, 14) 8.89mm 8.89mm
W (CFP, 14) 19.56mm × 6.67mm
FK (LCCC, 20) 9.21mm × 5.97mm
SN74AHC125 DB (SSOP, 14) 6.20mm 5.30mm
D (SOIC, 14) 8.65mm × 3.91mm
NS (SO, 14) 10.30mm × 5.30mm
DGV (TVSOP, 14) 3.60mm × 4.40mm
PW (TSSOP, 14) 5.00mm × 4.40mm
N (PDIP, 14) 19.30mm × 6.35mm
RGY (VQFN, 14) 3.50mm × 3.50mm
BQA (WQFN, 14) 3mm × 2.5mm
(1) For more information, see Section 11.
(2) The body size (length × width) is a nominal value and does not include pins.
GUID-8F3DA877-9F04-4CEB-B62F-692925279669-low.gif
Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages.
Logic Diagram (Positive Logic)