SCLSA04 March   2024 SN74AHC138-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Noise Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 Standard CMOS Inputs
      3. 7.3.3 Wettable Flanks
      4. 7.3.4 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Design Requirements
      1. 8.3.1 Power Considerations
      2. 8.3.2 Input Considerations
      3. 8.3.3 Output Considerations
    4. 8.4 Detailed Design Procedure
    5. 8.5 Application Curve
    6. 8.6 Power Supply Recommendations
    7. 8.7 Layout
      1. 8.7.1 Layout Guidelines
      2. 8.7.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1 Application Information

In this application, four 3-to-8 decoders are used to select l output from 32 using a 5-bit input as shown in Figure 8-1. The selected output is in the low state, while all other outputs are in the high state. One external inverter is required to complete the circuit.